Tuesday, December 31, 2019

5 #opensource innovation predictions for the 2020s and #4 is: "Quantum processors available for developers" https://t.co/xuyqACjisD https://t.co/hLcKH7QF5f


from Twitter https://twitter.com/wladek60

December 31, 2019 at 08:49AM
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Thursday, December 26, 2019

Researchers demo #CMOS-compatible #SOT #MRAM cell https://t.co/lbwzyuA5YE #paper https://t.co/5KIe9yJVaE


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December 26, 2019 at 11:46AM
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#paper K. Kato, H. Matsui, H. Tabata, M. Takenaka and S. Takagi, "Fabrication and Electrical Characteristics of ZnSnO/Si Bilayer Tunneling Filed-Effect Transistors" IEEE JEDS, vol. 7, pp. 1201-1208, 2019 doi: 10.1109/JEDS.2019.2933848 https://t.co/TrScHGouQR https://t.co/qizSOxCKSu


from Twitter https://twitter.com/wladek60

December 26, 2019 at 10:22AM
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Wednesday, December 25, 2019

Monday, December 23, 2019

#paper: Lee, M. Millimetre-scale thin-film batteries on a charge. Nat Electron 2, 550 (2019) doi:10.1038/s41928-019-0346-7 https://t.co/xzO5o0e6fl https://t.co/t5NHibezRc


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December 23, 2019 at 12:38PM
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#paper H. Hu et al., "A Compact Phase Change Memory Model With Dynamic State Variables," in IEEE TED. doi: 10.1109/TED.2019.2956193 https://t.co/PicLTsiRPy https://t.co/E2Knk0ZibS


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December 23, 2019 at 12:14PM
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Friday, December 20, 2019

Visualizing Moore’s Law in Action (1971-2019) https://t.co/jiCMsFxvVA #paper https://t.co/Ck0Pe8fHEz


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December 20, 2019 at 10:22PM
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#paper Si, M., Saha, A.K., Gao, S. et al. A #ferroelectric semiconductor field-effect transistor #FET. Nat Electron 2, 580–586 (2019) doi:10.1038/s41928-019-0338-7 https://t.co/DfLtGSLdrJ https://t.co/ZOMSORypoN


from Twitter https://twitter.com/wladek60

December 20, 2019 at 11:43AM
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EspoTek Labrador by EspoTek A small, portable, USB-connected electronics lab-on-a-board that includes an oscilloscope, waveform generator, power supply, logic analyzer, and multimeter. https://t.co/KjhalAzAZy #modeling https://t.co/CR1iTXYklY


from Twitter https://twitter.com/wladek60

December 20, 2019 at 09:39AM
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#paper Papadopoulos, N., Qiu, W., Ameys, M. et al. Touchscreen tags based on thin-film electronics #TFT for the Internet of Everything #IoT. Nat Electron 2, 606–611 (2019) doi:10.1038/s41928-019-0333-z https://t.co/EW6V32HgM2 https://t.co/5ZeCNzvssH


from Twitter https://twitter.com/wladek60

December 19, 2019 at 11:22PM
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Thursday, December 19, 2019

IEDM took place last week with: * Tutorials on Saturday * Two parallel short courses on Sunday * Plenary session on Monday morning * Press luncheon on Monday * Then a dozen sessions running in parallel https://t.co/hdrySfWNHf #paper https://t.co/0GxwGRMy0A


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December 19, 2019 at 03:48PM
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Wednesday, December 18, 2019

IRPhE 2020 Aghveran, Armenia

International Conference on Microwave & THz Technologies,
Wireless Communications and OptoElectronics
September 23-25, 2020, Aghveran, Armenia

IRPhE 2020 Call for Papers

The aim of the IRPhE’ 2020 Conference is to provide an open forum for the presentation and discussion of current research in Microwave and THz technologies, wireless communications, alternative electronic devices, photonics and its applications.

The main topics of the conference are and not limited to:

  • Microwave devices, antennas, propagation and remote sensing
  • THz technique, spectroscopy and applications
  • Alternative semiconductor and dielectric materials, electronic devices
  • Wireless communications and related information technologies
  • Microwave photonics
For further information visit the website: http://www.irphe.am/?q=conference

Submission Information
Original one page abstracts will be accepted for review in Word and PDF formats.The accepted abstracts will be published in an abstract book and distributed during the conference.
All the authors who have presented their work at the conference will be invited to submit 4-page follow-up papers for publication special IJHSES issue on the "Microwave and THz technologies"

Abstracts must be submitted via email: science@irphe.am.

Tuesday, December 17, 2019

Intel’s Manufacturing Roadmap from 2019 to 2029: Back Porting, 7nm, 5nm, 3nm, 2nm, and 1.4 nm; It’s worth also pointing out, based on the title of this slide, that #Intel still believes in #Moore’s Law. Just don’t ask how much it’ll cost. https://t.co/VIwrSoWEgB #paper https://t.co/LorF5xyHnT


from Twitter https://twitter.com/wladek60

December 17, 2019 at 12:03PM
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Monday, December 16, 2019

#paper Z. Ahmed, Q. Shi, Z. Ma, L. Zhang, H. Guo and M. Chan, "Analytical Monolayer MoS2 MOSFET Modeling Verified by First Principle Simulations," in IEEE EDL doi: 10.1109/LED.2019.2952382 https://t.co/CiaNcxqSwb https://t.co/xxTqg2iAMI


from Twitter https://twitter.com/wladek60

December 16, 2019 at 02:22PM
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The Open Source Computer Aided Modeling and Design #devroom schedule for #FOSDEM 2020 is official at: https://t.co/5GpDFo6fpo #paper https://t.co/dkTuVHseGP


from Twitter https://twitter.com/wladek60

December 16, 2019 at 11:13AM
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Wednesday, December 4, 2019

The EKV2.6 MOSFET compact #model has had a considerable impact on the academic and industrial community of ultra low power analog/RF IC design, since its inception in 1996. Its Verilog-A code is available online at GitHub, now https://t.co/0iDmBChDVm https://t.co/BTBAbPm7aN


from Twitter https://twitter.com/wladek60

December 04, 2019 at 03:23PM
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article reached 300 reads


W. Grabinski, D. Tomaszewski, L. Lemaitre and A. Jakubowski
Standardization of the compact model coding: non-fully depleted SOI MOSFET example
in Journal of Telecommunications and Information Technology

AbstractThe initiative to standardize compact (SPICE-like) modelling has recently gained momentum in the semiconductor industry. Some of the important issues of the compact modelling must be addressed, such as accuracy, testing, availability, version control, verification and validation. Most compact models developed in the past did not account for these key issues which are of highest importance when introducing a new compact model to the semiconductor industry in particular going beyond the ITRS roadmap technological 100nm node. An important application for non-fully depleted SOI technology is high performance microprocessors, other high speed logic chips, as well as analogue RF circuits. The IC design process requires a compact model that describes in detail the electrical characteristics of SOI MOSFET transistors. In this paper a non-fully depleted SOI MOSFET model and its Verilog-AMS description will be presented. 

Keywords: Verilog-AMS, compact model coding, SOI MOSFET.

Fig: Approximation of the distribution of currents components
in the non-fully depleted SOI MOSFET.  

Monday, December 2, 2019

[mos-ak] [Final Program] 12th International MOS-AK Workshop; Silicon Valley, Dec.11 2019

12th International MOS-AK Workshop
(co-located with the IEDM and Q4 CMC Meetings)
Silicon Valley, December 11, 2019

Together with Silvaco team, the MOS-AK workshop host as well as International MOS-AK Board of R&D Advisers and all the Extended MOS-AK TPC Committee, we have the pleasure to invite to consecutive, 12th International MOS-AK Workshop is Silicon Valley.

Scheduled, subsequent 12th MOS-AK SPICE/Compact Modeling Workshop organized in the Silicon Valley, aims to strengthen a network and discussion forum among experts in the field, enhance open platform for information exchange related to compact/SPICE modeling and Verilog-A standardization, bring people in the compact modeling field together, as well as obtain feedback from technology developers, circuit designers, and TCAD/EDA tool developers and vendors. 

The MOS-AK workshop program is available online:

Venue:
Silvaco 
2811 Mission College Blvd., 6th Floor 
Santa Clara, CA 95054

Online Registration is still open
(any related enquiries can be sent to register@mos-ak.org)

Postworkshop Publications:
Selected best MOS-AK technical presentation will be recommended for further publication
in a special 
Solid State Electronics issue on compact modeling 

W.Grabinski on the behalf of International MOS-AK Committee

WG02122019

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#Alibaba’s growing #opensource stature - Eyes on APAC https://t.co/W3qBN15Wsr https://t.co/DoR0OSzOMh


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December 02, 2019 at 04:07PM
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[C4P] 50th ESSDERC / 46th ESSCIRC

Grenoble (F) Sept.14-18 2020
Call for Papers

The aim of ESSCIRC and ESSDERC is to provide an annual European forum for the presentation and discussion of recent advances in solid-state devices and circuits. The level of integration for system-on-chip design is rapidly increasing. Therefore, more than ever before, a deeper interaction among technologists, device experts, IC designers and system designers is necessary. While keeping separate Technical Program Committees, ESSDERC and ESSCIRC are governed by a common Steering Committee and share Plenary Keynote Presentations and Joint Sessions bridging both communities. Attendees registered for either conference are encouraged to attend any of the scheduled parallel sessions, regardless to which conference they belong.

TPC Tracks:

  • Advanced Technology, Process and Materials
  • Analog, Power and RF Devices
  • Compact modeling and process/device simulation
  • Joint TRACK: Memory devices and circuits towards non Von Neumann
  • Joint TRACK: Emerging Computing Devices and Circuits
  • Joint TRACK: Devices and circuits for Sensors, Optoelectronics and Display
  • Analog Circuits
  • Data Converters Circuits
  • RF & mmW Circuits
  • Frequency Generation Circuits
  • Wireless & Wireline Circuits & Systems
  • Digital Circuits & Systems
  • Power Management Circuits