Jun 17, 2019

[open source paper] Open-source circuit simulation tools for RF compact semiconductor device modelling

Open-source circuit simulation tools for RF compact semiconductor device modelling
Wladek Grabinski (editor), Mike Brinson, Paolo Nenzi, Francesco Lannutti, Nikolaos Makris, Angelos Antonopoulos and Matthias Bucher
September 2014
DOI: 10.1002/jnm.1973

SUMMARY: MOS-AK is a European, independent compact modelling forum created by a group of engineers, researchers and compact modelling enthusiasts to promote advanced compact modelling techniques and model standardization using high level behavioral modelling languages such as VHDL-AMS and Verilog-A. This invited paper summarizes recent MOS-AK open source compact model standardization activities and presents advanced topics in MOSEFT modelling, focusing in particular on analogue/RF applications. The paper discusses links between compact models and design methodologies, finally introducing elements of compact model standardization. The open source CAD tools: Qucs, QucsStudio and ngspice all support Verilog-A as a hardware description language for compact model standardization. Latter sections of this paper describe a Verilog-A implementation of the EKV3 MOS transistor model. Additionally, the simulated  RF model performance is evaluated and compared with experimental results for 90nm CMOS technology. 

KEYWORDS: CAD; GNU; Qucs; QucsStudio; ngspice; compact modeling; EKV3; RF; MOSFET; Verilog-A

Jun 14, 2019

[book] POWER/HVMOS Devices Compact Modeling


POWER/HVMOS Devices Compact Modeling 
Wladyslaw Grabinski and Thomas Gneiting

Book 7 Citations;   119 Readers;   2 Reviews;   6k+ Downloads
DOI: 10.1007/978-90-481-3046-7

Since its online publication on Jun 10, 2010, there have been a total of 6452 chapter downloads for your eBook on SpringerLink. The table below shows the download figures for the last years:


Jun 11, 2019

[mos-ak] [Final Program] 4th Sino MOS-AK Workshop Chengdu, June 20-22, 2019

4th Sino MOS-AK Workshop 
UESTC 电子科技大学 Chengdu, June 20-22, 2019 

Together with local host Prof. Yuhang Xu, UESTC 电子科技大学 and coordinating organizer Dr. Min Zhang, XMOD as well as all the Extended MOS-AK TPC Committee, we have pleasure to invite to consecutive, 4th Sino MOS-AK Workshop at UESTC 电子科技大学 Chengdu, between June 20-22, 2019

After successful series of MOS-AK workshops in Shanghai, Hangzhou and Beijing, our next scheduled, subsequent 4th Sino MOS-AK Workshop at UESTC 电子科技大学 Chengdu, aims to strengthen a network and discussion forum among experts in the field, enhance open platform for information exchange related to compact/SPICE modeling and its Verilog-A standardization, bring people in the compact modeling field together, as well as obtain feedback from technology developers, circuit designers, and TCAD/EDA tool developers and vendors. The MOS-AK workshop program is available online: <http://www.mos-ak.org/chengdu_2019/> (see also below)

UESTC Library Realistic office (the second floor of the museum next to the library)

Online Registration is still open
 (any related enquiries can be sent to Yuan Yao mobile:13086679508)

Postworkshop Publications:
Selected best MOS-AK technical presentation will be recommended for further publication
in a special issue of the International Journal of High Speed Electronics and Systems

Recommended hotels
Hotel: Holiday Inn Chengdu High-Tech Center
Address: No.1-1 Xixin Avenue Pidu District Chengdu China

Prof. Yuhang Xu, UESTC
Dr. Min Zhang, XMOD
and W.Grabinski

Final MOS-AK Program Announcement
20th JUNE MOS-AK Tutorial Day
9:00-11:45 Modeling of Silicon-Germanium Heterojunction Bipolar Transistors for mm-Wafer circuits
Andreas Pawlak
Infineon AG
13:00-16:15 1. Radar frontends for ranging and speed measurements operating at 24GHz, 60GHz and 122GHz ISM frequency bands 
2. Radar frontends for MIMO radars operating at 24GHz, 60GHz, 122GHz and 245GHz ISM frequency bands
Wojciech Debski 
Silicon Radar GmbH
21st JUNE 1st Day of MOS-AK Workshop
9:30-9:35  MOS-AK Opening Speech
9:35-9:40 MOS-AK Review & Outlook
Min Zhang, Wladek Grabinski
9:40-10:25 The Model and Algorithm Prototyping Platform (invited talk)
Jaijeet Roychowdhury
10:25-10:50 Device modeling Eco-system Driven by Learning-based algorithms
Yanfeng Li
10:50-11:05 Tea break
11:05-11:50 Simulation and Modeling of Dynamic Systems with Time Varying device Characteristics (invited talk)
Masun Chan
11:50-12:00 Group photo
12:00-13:30 Lunch 
13:30-14:00 Advanced TFT Modeling Techniques for GOA Driver Circuit Design Optimization (invited talk)
An-Thung Cho, Lifeng Wu
HuaDa Empyrean software, Chongqing HKC
14:00-14:25 Active Device Channel spice thermal modeling and parameter extraction 
Fujiang Lin
14:25-14:50 Simulation-Based Reliability Analysis for Advanced Designs and Applications
Xugang Shen
Synopsys, Inc.
14:50-15:10 Tea break
15:10-15:55 Silicon intergrated magneto-optical nonreciprocal photonic devices (invited talk)
Lei Bi
15:55-16:20 An Analysis of DG SOI MOSFET Modeling and Simulation with PSP, BSIM-IMG and HiSIM_SOTB
GuoFang Wang, Jun Liu
16:20-16:45 TCAD-Based Statistical Modelling Methodology for Nanoscale FinFET Variability
Guo Ao
16:45-17:10 Characterization and Modeling of the Reverse behavior of a Vertical Power MOSFET
Lixi Yan
Stuttgart University
17:10-17:35 An Industry Standard Model Including Fast and Extended Range Core with Improved Mobility and Noise effect
Chetan Kumar Dabhi
17:35-18:30MOS-AK Compact Modeling Round-Table Forum
Min Zhang, Wladek Grabinski
18:30-20:00 MOS-AK Gala Dinner
22nd JUNE 2nd Day of MOS-AK Workshop
9:30-10:15 Negative Capacitance FET and Nanowire/Nanosheet FET modeling (invited talk)
Yogesh Chauhan
10:15-10:40 An Simulation Platform for IGBT Module Electrothermal Analysis
Chen Shen
10:40-11:00 Tea break
11:00-11:45 Artificial Neural Networks for Microwave Modeling and Design (invited talk) 
Qijun Zhang
Carleton University
11:45-12:10 A transient ionizing Radiation Spice model for PDSOI MOSFET
Jianhui Bu
IME Chinese Academy
12:10-13:30 Lunch 
13:30-14:15 Quasi-physical Zone division (QPZD) model for microwave wide-band-gap semiconductor technology (invited talk)
Yuehang Xu
14:15-14:40 RF GaN Device model survey and model parameter extraction flows
Raj Sodhi
14:40-15:05 Charaterization and modeling of Memory effects for GaN HEMTs
ZhiFu Hu 
15:05-15:25 Tea break
15:25-15:50 Key Technology to GaN-based mm-Wave Devices and MMIC's (invited talk)
Xiaohua Ma
Xidian University
15:50-16:15 A Dimension-Reduction Method for the Thermal Modeling of InGaP/GaAs HBTs
Wenrui Hu, Yongxin Guo
16:15-16:40 DC and RF Modeling of CMOS Schottky Diodes 
Wenyuan Zhang, Yan Wang
Tsinghua University
16:45-17:10 RF GaN Device modeling for MMIC design
Chujun Wang
17:10-17:15 MOS-AK 2020
Min Zhang, Wladek Grabinski
End of the MOS-AK Chengdu Workshop

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S. Li etal. A Buffer-Less Wideband Frequency Doubler in 45nm SOI with Transistor Multi-Port Waveform Shaping Achieving 25% Drain Efficiency and 46-89GHz Instantaneous Bandwidth in IEEE Solid-State Circuits Letters. doi: 10.1109/LSSC.2019.2918943 https://t.co/buZkWbSAvo #paper https://t.co/dEPj5OG5Vb

from Twitter https://twitter.com/wladek60

June 11, 2019 at 02:22PM

Jun 6, 2019

You Don’t Need That Bulky CRT #Oscilloscope Anymore https://t.co/UFW4yYoPcS #opensource https://t.co/CqVdDKnPQr

from Twitter https://twitter.com/wladek60

June 06, 2019 at 12:06PM

Modeling Emerging Semiconductor Devices for Circuit Simulation https://t.co/QMvNfZ9vsl #paper https://t.co/1gWFMFxzmq

from Twitter https://twitter.com/wladek60

June 06, 2019 at 10:03AM

[paper] Novel General Compact Model Approach

A Novel General Compact Model Approach for 7nm Technology Node Circuit Optimization from Device Perspective and Beyond

Qiang Huo, Zhenhua Wu, Weixing Huang, Xingsheng Wang, Senior Member, IEEE, Geyu Tang, Jiaxin Yao, Yongpan Liu, Feng Zhang, Ling Li, and Ming Liu, Fellow,IEEE

Abstract: This work presents a novel general compact model for 7nm technology node devices like FinFETs. As an extension of previous conventional compact model that based on some less accurate elements including one-dimensional Poisson equation for three-dimensional devices and analytical equations for short channel effects, quantum effects and other physical effects, the general compact model combining few TCAD calibrated compact models with statistical methods can eliminate the tedious physical derivations. The general compact model has the advantages of efficient extraction, high accuracy, strong scaling capability and excellent transfer capability. As a demo application, two key design knobs of FinFET and their multiple impacts on RC control ESD power clamp circuit are systematically evaluated with implementation of the newly proposed general compact model, accounting for device design, circuit performance optimization and variation control. The performance of ESD power clamp can be improved extremely. This framework is also suitable for pathfinding researches on 5nm node gate-all-around devices, like nanowire (NW) FETs, nanosheet (NSH) FETs and beyond.

Index Terms: General compact model, FinFET, ESD power clamp, 7 nm technology node and beyond.

Fig. (A) The schematic of partial parameters of FinFET. (B) Key design rules of 7nm node FinFET as according to [1]. 

Access: https://arxiv.org/ftp/arxiv/papers/1905/1905.11207.pdf

REF: [1] S. Narasimha et al.“A 7nm CMOS technology platform for mobile and high performance compute application,” IEEE International Electron Devices Meeting (IEDM), Dec. 2017, pp. 29.5.1-29.5.4, doi: 10.1109/IEDM.2017.8268476.

[paper] Analogue and RF performances of Fully Depleted SOI MOSFET

Jean-Pierre Raskin1
1Institute of Information and Communication Technologies, Electronics and Applied Mathematics (ICTEAM), Université catholique de Louvain (UCLouvain), Place du Levant, 3, Maxwell Building, bte L5.04.04, office B.327, B-1348 Louvain-la-Neuve, Belgium
ABSTRACT. Performance of RF integrated circuit (IC) is directly linked to the analogue and high frequency characteristics of the transistors, the quality of the back-end of line process as well as the electromagnetic properties of the substrate. Thanks to the introduction of the trap-rich high-resistivity Silicon-on-Insulator (SOI) substrate on the market, the ICs requirements in term of linearity are fulfilled. Today Partially Depleted (PD) SOI MOSFET is the mainstream technology for RF SOI systems. Future generations of mobile communication systems will require transistors with better high frequency performance operating at lower power consumption and in the millimeter-waves range. Fully Depleted (FD) SOI MOSFET is a quite promising candidate for the development of these future wireless communication systems. Most of the reported data on FD SOI concern their digital performance. In this paper, their analogue/RF behaviour is described and compared with bulk MOSFETs. Self-heating issue, non-linear behaviour as well as high frequency performance at cryogenic temperature for FD SOI MOSFET are discussed. Finally, a brief summary of the published RF and millimeter-waves ICs based on FD SOI technology is presented.

KEYWORDS. Silicon-on-Insulator (SOI), Fully Depleted (FD), high frequency behaviour, Radio Frequency (RF), millimeter-waves, analogue/RF performances, self-heating, non-linear behaviour, cryogenic temperature, Integrated Circuits (ICs).

FIG: Simplified cross section of FD SOI nMOSFET with back-gate (BGN).

ACCESS: http://www.openscience.fr/IMG/pdf/iste_componano19v2n1_5.pdf