[PhD] Transient Simulation of Frequency Domain Devices in Gnucap

Adding transient simulation of frequency domain devices to the Gnucap circuit simulator

Phd Thesis by Seán Higginbotham

Supervisor: Assistant Prof. Justin King

April 2024

Trinity College Dublin, The University of Dublin

College Green, Dublin 2, Ireland

Abstract: Radio frequency design constitutes a dominant element in the development of key communications technologies. Having accurate, robust, and widely accessible simulation methods is critical to ensuring continued advancements in this field, and guaranteeing the associated infrastructural and societal shifts that such technologies enable.

High frequency circuits invariably contain multiple non-linear components, which are naturally dealt with via time marching simulation of their time-domain analytic equations. However, including this alongside linear, generally dispersive, devices and effects, which are typically only characterised through a set of frequency-domain data describing the scattering response of an associated port-network, has traditionally been a problem for designers. Frequency-domain methods such as the harmonic balance technique and its successors have dominated radio frequency design for decades. However, such methods exhibit disadvantages in the context of modern circuits which are increasingly non-linear, and which operate with increasingly complicated modulated signals.

Various alternatives have been proposed, though as of yet no universally accepted method has emerged. Though harmonic balance will likely not be replaced, this project seeks to implement one such pure transient technique as an alternative. The proposed technique is based on using the vector-fitting algorithm to produce a model of the frequency response of the linear portnetwork, and then using a recursive convolution formulation to allow the time-domain response to be efficiently obtained from the port’s impulse response. An equivalent circuit companion model is developed from the resulting time-domain power-wave relation. This companion model allows the linear device to be directly included in a transient simulation alongside the analytic non-linear components, by way of providing a manner of computing the voltage and current on the network’s ports.

We implement the technique for one-port networks in a circuit driven by baseband signals. It is added to the free, open-source Gnucap circuit simulator as a ‘device plugin’. This report details how the implementation was done and provides results illustrating that it works as intended; the plugin can be installed by a user, who simply provides it with a file of frequency-domain data representing the port-network, and the plugin works naturally with the Gnucap transient solver to allow obtaining a transient solution of the overall circuit. A pure transient technique such as this does not require limiting assumptions or approximations on any components in the circuit and they are therefore preferable in certain contexts to frequency-domain methods like harmonic balance.

The project offers a significant contribution towards increasing the accessibility of radiofrequency electronics design and teaching.

 FIG: Summary of the traditional approach to simulating RF/MW circuits via HB, and the proposed pure transient approach implemented in this PhD Thesis

Acknowledgements: Seán Higginbotham would like to thank my M.A.I supervisor Dr. Justin King, whose previous work was the basis for this project. He provided invaluable insights and guidance which made the project both possible and an enjoyable experience, instilling curiosity at each discussion. Relevant academic references are included in the bibliography section. Acknowledgements of the dependancies used in the project code follow.

Gnucap is the creation of Albert Davis and is developed by him and others. It is provided under the GNU GPLv3, which is also the license that this project code is provided under on the associated GitHub repository.

See https://www.gnu.org/licenses/gpl-3.0.html. For the GNU GPLv3 license. Additionally, see the Gnucap repository here https://savannah.gnu.org/projects/ gnucap/.

LAPACK is a co-creation of The University of Tennessee and The University of Tennessee Research Foundation, The University of California Berkeley, and The University of Colorado Denver. See the user guide here https://netlib.org/lapack/.

The LAPACKE C bindings are the creation of Intel Corp.

The relevant licensing files are found within the source code and on the respective website.

Should the reader of this report have any questions or suggestions, please feel free to reach out at higginbs@tcd.ie, or via other channels such as the project GitHub located at https: //github.com/SHigginbotham/transient-sparam-gnucap. The project supervisor may also be of interest, available at justin.king@tcd.ie.

[paper] Neural Compact Modeling Framework

Eom, Seungjoon, Hyeok Yun, Hyundong Jang, Kyeongrae Cho, Seunghwan Lee, Jinsu Jeong, and Rock‐Hyun Baek

Neural Compact Modeling Framework for Flexible Model Parameter Selection with High Accuracy and Fast SPICE Simulation

Advanced Intelligent Systems (2023): 2300435

DOI: 10.1002/aisy.202300435

Department of Electrical Engineering, Pohang University of Science and Technology, Pohang 37673 (KR)

Abstract: Neural compact models are proposed to simplify device-modeling processes without requiring domain expertise. However, the existing models have certain limitations. Specifically, some models are not parameterized, while others compromise accuracy and speed, which limits their usefulness in multi-device applications and reduces the quality of circuit simulations. To address these drawbacks, a neural compact modeling framework with a flexible selection of technology-based model parameters using a two-stage neural network (NN) architecture is proposed. The proposed neural compact model comprises two NN components: one utilizes model parameters to program the other, which can then describe the current–voltage (IV) characteristics of the device. Unlike previous neural compact models, this two-stage network structure enables high accuracy and fast simulation program with integrated circuit emphasis (SPICE) simulation without any trade-off. The IV characteristics of 1000 amorphous indium–gallium–zinc-oxide thin-film transistor devices with different properties obtained through fully calibrated technology computer-aided design simulations are utilized to train and test the model and a highly precise neural compact model with an average IDS error of 0.27% and R2 DC characteristic values above 0.995 is acquired. Moreover, the proposed framework outperforms the previous neural compact modeling methods in terms of SPICE simulation speed, training speed, and accuracy.

Fig: a) The structure of a-IGZO TFT structure simulated with TCAD

b) Calibrated a-IGZO sub-gap DOS

Acknowledgements: This work was supported in part by the LG Display Company, in part by the Brain Korea 21 Fostering Outstanding Universities for Research (BK21 FOUR) program, in part by Institute of Information and Communications Technology Planning and Evaluation (IITP) grant funded by the Korea government (MSIT) (grant no. 2019-0-01906, Artificial Intelligence Graduate School Program [POSTECH]), in part by the Ministry of Trade, Industry and Energy (MOTIE) under grant no. 20020265, in part by Korea Semiconductor Research Consortium (KSRC) support program for the development of the future semiconductor device, and in part by the Technology Innovation Program (grant no. RS2023-00231985) funded by the Ministry of Trade, Industry and Energy (MOTIE, Korea) (grant no. 1415187390).

[review] TCAD Simulations of Semiconductor Piezoresistance

Takaya Sugiura, Kazunori Matsuda*, Nobuhiko Nakano

Review: Numerical Simulations of Semiconductor Piezoresistance for Computer-Aided Designs

in IEEE J-EDS, vol. 11, pp. 325-336, 2023

DOI: 10.1109/JEDS.2023.3281866

  Department of Electronics and Electrical Engineering, Keio University, Yokohama, Kanagawa, Japan

* Division of Electrical, Electronic and Infocommunications Engineering, Osaka University, Suita, Japan

Abstract: The field of piezoresistance has mainly advanced through experimental research; however, the improved accuracy of simulations and the emergence of new materials have increased the importance of simulations in this field. This review discusses the methods and current topics related to simulations of piezoresistive devices. Advancing simulation modeling will facilitate the computer-aided design of piezoresistive devices, and this review introduces the means of establishing these models by discussing the current studies on simulations and calculations in this field. Two simulation methods currently exist namely, device simulations and first-principles theoretical analysis. This review focuses on numerical simulation approaches for modeling of the piezoresistive effect using the multiphysics simulations of the mechanical and electrical behaviors of piezoresistive materials.

FIG: Basic simulation flow for studies on semiconductor piezoresistors.

[book] Circuit Simulation and Modeling with Phyton

Circuit Simulation and Modeling with Phyton

Hardcover – April 9, 2021

by Kenji Mori (author), Akira Matsuzawa (author)

This book is written for people who are learning Python. Circuit simulation and modeling are selected as subjects for programming using Python. The process of building a net" is attached to Chapter 5 appendix "Diode/MOSFET Coding Flow Diagram". Text Python source code suitable for learning by students and companies / corporations can be downloaded from the web.

About the Authors

Akira Matsuzawa: Professor Emeritus, Tokyo Institute of Technology President of Tech Idea Co., Ltd. 1978; Completed master's course at Graduate School of Engineering, Tohoku University. Joined Matsushita Electric Industrial (now Panasonic) in the same year 1997; Completed doctoral program at Graduate School of Engineering, Tohoku University 2003; Professor, Graduate School of Science and Engineering, Tokyo Institute of Technology 2018 Retired from Tokyo Institute of Technology Professor Emeritus at the same university

His books:
"First analog electronic circuit basic circuit edition" Kodansha (2015)
"First Analog Electronic Circuit Practical Circuit Edition" Kodansha (2016)
"Analog RFCMOS Integrated Circuits Basic Edition" Baifukan (2010)
"Analog RFCMOS Integrated Circuits Application Edition" Baifukan (2011)
"Learning Circuit Simulation and Modeling with MATLAB" Torikagesha (2020)

Kenji Mori: Part-time Lecturer, Tokyo Institute of Technology March 1979. Graduated from Tokushima University Graduate School of Electrical Engineering, joined NEC Corporation in the same year, engaged in circuit simulator development, automatic filter design program development, and circuit check program development. Joined Nippon Steel Corporation in November 1990, engaged in parameter extraction of MOSFET models. April 2009 Developed a prototype program for automatic design of mixed-signal LSI with Mr. Sugawara, an industry-academia-government collaboration researcher at Tokyo Institute of Technology. April 2014 Part-time Lecturer, Tokyo Institute of Technology

His books:
"Circuit Simulation Technology and MOSFET Modeling" Realize Riko Center (2003)
"Learning Circuit Simulation and Modeling with MATLAB" Torikagesha (2020)

[paper] p-Type Doped Silicene-based

Mu Wen Chuan, Munawar Agus Riyadi, Afiq Hamzah, Nurul Ezaila Alias, Suhana Mohamed Sultan, Cheng Siong Lim, Michael Loong Peng Tan

Device performances analysis of p-type doped silicene-based field effect transistor using SPICE-compatible model

PLoS ONE 17(3): e0264483.: March 3, 2022

DOI: 10.1371/journal.pone.0264483

   
Universiti Teknologi Malaysia, Skudai, Johor, Malaysia
Diponegoro University, Semarang, Indonesia

Abstract: Moore’s Law is approaching its end as transistors are scaled down to tens or few atoms per device, researchers are actively seeking for alternative approaches to leverage more-than-Moore nanoelectronics. Substituting the channel material of a field-effect transistors (FET) with silicene is foreseen as a viable approach for future transistor applications. In this study, we proposed a SPICE-compatible model for p-type (Aluminium) uniformly doped silicene FET for digital switching applications. The performance of the proposed device is benchmarked with various low-dimensional FETs in terms of their on-to-off current ratio, subthreshold swing and drain-induced barrier lowering. The results show that the proposed p-type silicene FET is comparable to most of the selected low-dimensional FET models. With its decent performance, the proposed SPICE-compatible model should be extended to the circuit-level simulation and beyond in future work.

Fig: Schematic diagrams of AlSi3 FET: (a) the structure and 

(b) the ToB nanotransistor circuit model. 

Acknowledgements: 1.) Michael Tan Loong Peng - Ministry of Higher Education (MOHE) of Malaysia through the Fundamental Research Grant Scheme(FRGS/1/2021/ STG07/ UTM/02/3); The funders had no role in study design, data collection and analysis, decision to publish, or preparation of the manuscript. 2.) Munawar Agus Riyadi - World Class Research Universitas Diponegoro (WCRU) 2021 Grant no. 118-16/UN7.6.1/PP/2021; The funders had no role in study design, data collection and analysis, decision to publish, or preparation of the manuscript.

[paper] Circuit-Based Compact Model of Electron Spin Qubit

Mattia Borgarino

Circuit-Based Compact Model of Electron Spin Qubit

Special Issue Recent Advances in Silicon-Based RFIC Design;

Electronics 2022, 11(4), 526; 

DOI: 10.3390/electronics11040526

   
University of Modena and Reggio Emilia, Modena (IT)

Abstract: Today, an electron spin qubit on silicon appears to be a very promising physical platform for the fabrication of future quantum microprocessors. Thousands of these qubits should be packed together into one single silicon die in order to break the quantum supremacy barrier. Microelectronics engineers are currently leveraging on the current CMOS technology to design the manipulation and read-out electronics as cryogenic integrated circuits. Several of these circuits are RFICs, as VCO, LNA, and mixers. Therefore, the availability of a qubit CAD model plays a central role in the proper design of these cryogenic RFICs. The present paper reports on a circuit-based compact model of an electron spin qubit for CAD applications. The proposed model is described and tested, and the limitations faced are highlighted and discussed.

FIG: Compact model of the electron spin qubit.

Funding: This research received no external funding.

[paper] SPICE simulation of PIN diodes and IGBT devices

Manhong Zhang, Yi Zhai

Recovering the carrier number conservation in SPICE simulation of PIN diodes and IGBT devices

Solid-State Electronics

Available online 7 February 2022, 108239

DOI: 10.1016/j.sse.2022.108239

   
North China Electric Power University, Beijing 102206, China

Abstract: In SPICE simulations of PIN diodes and IGBT devices using finite difference method, one discretizes an undepleted N- region into several equally spaced nodes with a time-dependent distance of Δx(t). Then transforms the ambipolar diffusion equation, a time-space partial differential equation, into a set of time-dependent ordinary differential equations. However, the time-dependent property of Δx(t) destroys the carrier number conservation. In this paper, we propose an approach to account for the effect of the Δx(t) by introducing an auxiliary system. It has the same total current and the total carrier number in the undepleted N- region as the real system, but has different electron and hole current components. The difference is caused by adding compensation current terms with the equal amplitude and opposite sign to the electron and hole current terms in the auxiliary system. These compensation current terms are proportional to the boundary speed of the undepleted N- region and do not change the total current. The auxiliary system can be easily solved using SPICE behavior models and its carrier density is a good approximation to the real one. Our simulations show that the compensation current correction is important for fast switching PIN diodes, but may not be very important in IGBT devices due to their large gate-related capacitance.

FIG: SPICE simulation model of PIN diodes and IGBT devices

[book] Nano Interconnects: Device Physics, Modeling and Simulation

Afreen Khursheed and Kavita Khare

Nano Interconnects: Device Physics, Modeling and Simulation

CRC Press; 1st edition (2021)

ISBN: ‎ 978-0367610487

This textbook comprehensively covers on-chip interconnect dimension and application of carbon nanomaterials for modeling VLSI interconnect and buffer circuits. It provides analysis of ultra-low power high speed nano-interconnects based on different facets such as material modeling, circuit modeling and the adoption of repeater insertion strategies and measurement techniques. It covers important topics including on-chip interconnects, interconnect modeling, electrical impedance modeling of on-chip interconnects, modeling of repeater buffer and variability analysis. Pedagogical features including solved problems and unsolved exercises are interspersed throughout the text for better understanding. Aimed at senior undergraduate and graduate students in the field of electrical engineering, electronics and communications engineering for courses on Advanced VLSI Interconnects, Advanced VLSI Design, VLSI Interconnects, VLSI Design Automation and Techniques, this book:

• Provides comprehensive coverage of fundamental concepts related to nanotube transistors and interconnects.
• Discusses properties and performance of practical nanotube devices and related applications.
• Covers physical and electrical phenomena of carbon nanotubes, as well as applications enabled by this nanotechnology.
• Discusses the structure, properties, and characteristics of graphene-based on-chip interconnect.
• Examines interconnect power and interconnect delay issues arising due to downscaling of device size.

[paper] Bridging the gap between design and simulation of low voltage CMOS circuits

C. M. Adornes, D. G. Alves Neto, M. C. Schneider and C. Galup-Montoro

Bridging the gap between design and simulation of low voltage CMOS circuits

2021 IEEE Nordic Circuits and Systems Conference (NorCAS), 2021, pp. 1-5,

DOI: 10.1109/NorCAS53631.2021.9599867

Abstract: This work proposes a simplified MOSFET model based on the Advanced Compact MOSFET (ACM) model, which contains only four parameters to assist the designer in understanding how the main MOSFET parameters affect the design. The 4-parameter model was implemented in Verilog-A to simulate different circuits designed with the ACM model. A CMOS inverter and a ring oscillator were designed and simulated, either using the 4-parameter ACM model or the BSIM model. The simulation results demonstrate that the 4-parameter model is very suitable for ultra-low-voltage (ULV) modeling. In the ultra-low-voltage domain, some of the secondary effects of the MOSFET are not relevant and thus not included in the 4-parameter model. A simplified MOSFET model for the ULV domain is of great importance to applications such as energy harvesting, sensor nodes for the Internet of Things, and always-on circuits.

C. M. Adornes Video Presentation NorCAS 2021

Acknowledgment: The authors would like to thank the Brazilian agencies CAPES, finance code 001, and CNPq for supporting this work.

REF:

[1] A. I. A. Cunha, M. C. Schneider and C. Galup-Montoro, "An MOS Transistor Model for Analog Circuit Design", IEEE J. Solid-State Circuits, vol. 33, no. 10, pp. 1510-1519, October 1998

[2] C. Galup-Montoro and M. C. Schneider, "The compact all-region MOSFET model: theory and applications", IEEE 16th International New Circuits and Systems Conference (NEWCAS), pp. 166-169, June 2018

[3] M. C. Schneider and C. Galup-Montoro, CMOS Analog Design Using All-Region MOSFET Modeling, Cambridge University Press, 2010

[4] C. Galup-Montoro and M. C. Schneider, MOSFET modeling for circuit analysis and design, World Scientific, 2007

[5] Verilog-A Reference Manual, Agilent Technologies, 2004

[6] 0. F. Siebel, "Um modelo eficiente do transistor MOS para o projeto de circuitos VLSI," Universidade Federal de Santa Catarina, Florianopolis, 2007

[7] F. N. Fritsch, R. E. Shafer and W. P. Crowley, "Algorithm 443: Solution of the transcendental equation wew=x," Commun. ACM, vol. 16, no. 2, pp. 123-124, 1973

[8] O. F. Siebel, M. C. Schneider and C. Galup-Montoro, "MOSFET threshold voltage definition, extraction and some applications," Microelectronics Journal, vol. 43, no. 5, pp. 329-336, May 2012

[9] G. Hiblot. DIBL-Compensated Extraction of the Channel Length Modulation Coefficient in MOSFETS. IEEE Transactions on Electron Devices, vol. 65, no. 9, pp. 4015-4018, 2018

[10] BSIM4v4.5.0 Technical Manual, Department of Electrical Engineering and Computer Science, UC Berkeley, Berkeley, CA, USA. 2004

[11] Y. Tsividis and C. McAndrew, Operation and Modeling of the MOS Transistor, Oxford Univ. Press, 2011

[12] J. V. T. Ferreira, C. Galup-Montoro, "Ultra-low-voltage CMOS ring oscillators. Electronics Letters," IET, v. 55, n. 9, p. 523-525,2019

[13] E. M. Camacho-Galeano, C. Galup-Montoro and M. C. Schneider, "A 2-nW 1.1.-V self biased current reference in CMOS technology," IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 52, no. 2, pp. 61-65, 2005

[14] E. Bolzan, E. B. Storck, M. C. Schneider and C. Galup-Montoro, "Design and testing of a CMOS SelfBiased Current Source," 2019 26th IEEE International Conference on Electronics, Circuits and Systems (ICECS), pp. 382-385, 2019

Circuit Design and Simulation Marathon using eSIM

 

Indian Institute of Technology, Bombay

We are happy to announce the first ever #Circuit #Design and #Simulation #Marathon using #eSim! This event is jointly organized by #FOSSEE and VLSI System Design. The FOSSEE project developed at Indian Institute of Technology, Bombay is powered by MINISTRY OF EDUCATION, GOVERNMENT OF INDIA.

To know more about the Circuit Design and Simulation Marathon, please visit https://hackathon.fossee.in/esim/

Important dates:
>> Registration: 21 May 2021 - 15 June 2021
>> Marathon Launch : 17 June 2021

[paper] GaN-HEMT Compact Model

Ke Li¹, Paul Leonard Evans², Christopher Mark Johnson², Arnaud Videt³, and Nadir Idir³

A GaN-HEMT Compact Model Including Dynamic RDSon Effect

for Power Electronics Converters

MDPI Energies 2021, 14, 2092.

DOI: 10.3390/en14082092

1 Centre for Advanced Low-Carbon Propulsion Systems, Coventry University, Coventry CV1 2TL, UK
2 Power Electronics, Machines and Control Group, University of Nottingham, Nottingham NG7 2RD, UK;
3 Laboratoire d’Electrotechnique et d’Electronique de Puissance, Université de Lille, France;

Abstract: In order to model GaN-HEMT switching transients and determine power losses, a compact model including dynamic RDSon effect is proposed herein. The model includes mathematical equations to represent device static and capacitance-voltage characteristics, and a behavioural voltage source, which includes multiple RC units to represent different time constants for trapping and detrapping effect from 100 ns to 100 s range. All the required parameters in the model can be obtained by fitting method using a datasheet or experimental characterisation results. The model is then implemented into our developed virtual prototyping software, where the device compact model is co-simulated with a parasitic inductance physical model to obtain the switching waveform. As model order reduction is applied in our software to resolve physical model, the device switching current and voltage waveform can be obtained in the range of minutes. By comparison with experimental measurements, the model is validated to accurately represent device switching transients as well as their spectrum in frequency domain until 100 MHz. In terms of dynamic RDSon value, the mismatch between the model and experimental results is within 10% under different power converter operation conditions in terms of switching frequencies and duty cycles, so designers can use this model to accurately obtain GaN-HEMT power losses due to trapping and detrapping effects for power electronics converters.

Fig: GaN-HEMT device structure and its compact model

Acknowledgments: The authors would like to acknowledge Loris Pace for technical discussions and experimental support. This research was funded by the UK Engineering and Physical Sciences Research Council (EPSRC) through research grant [EP/K035304/1 and EP/R004390/1] and French State Region Plan Contract Intelligent Integrated Energy Converter (CPER-CE2I) project.

[C4P] DevIC 2021

DevIC 2021: Call for Papers

IEEE KGEC Student Branch Chapter in association with Department of ECE, KGEC, technically co-sponsored by IEEE EDS Kolkata Chapter  organizes International conference 4th Int. Conference DevIC 2021 “Devices for Integrated Circuit (DevIC)”.  There will be keynote lectures/talks, tutorials, and oral presentations  by eminent researchers. The conference organizers invite original papers in the research areas of various aspects of semiconductor technology and circuits that creates an opportunity to symbiosis on topic ranging from process technology to system-on-chip. Articles announcing significant and original results are highly requested. Papers are solicited across the general field of electronic devices. Topics of interest include, but are not limited to;

• CMOS Processes, Devices and Integration;
• VLSI Technology and Circuits;
• Innovative Systems;
• Emerging Non-CMOS Devices & Technologies;
• Device Modelling & Simulation; 
• Device Characterization, Reliability & Yield; 
• Devices with New material systems;
• Devices for Low power applications;
• Low dimensional devices;
• Low dimensional Semiconductors; 
• Design and Simulation of Circuits with nanoscale devices;
• MEMS, Sensors & Display Technologies;
• Advanced & Emerging Memories; 
• High frequency wireless communication;

DevIC 2021 Conference Committee

[paper] Scaled GaN-HEMT Large-Signal Model Based on EM Simulation

Scaled GaN-HEMT Large-Signal Model Based on EM Simulation

Wooseok Lee¹, Hyunuk Kang¹, Seokgyu Choi², Sangmin Lee², Hosang Kwon³, Keum cheol Hwang¹, Kang-Yoon Lee¹ and Youngoo Yang¹

Electronics 2020, 9(4), 632

DOI: 10.3390/electronics9040632

¹Department of Electrical and Computer Engineering, Sungkyunkwan University, Suwon 16419, Korea
²Wavice Inc., Hwaseong-si 18449, Korea
³Agency for Defense Development, Daejeon 34186, Korea

Abstract This paper presents a scaled GaN-HEMT large-signal model based on EM simulation. A large-signal model of the 10-finger GaN-HEMT consists of a large-signal model of the two-finger GaN-HEMT and an equivalent circuit of the interconnection circuit. The equivalent circuit of the interconnection circuit was extracted according to the EM simulation results. The large-signal model for the two-finger device is based on the conventional Angelov channel current model. The large-signal model for the 10-finger device was verified through load-pull measurement. The 10-finger GaN-HEMT produced an output power of about 20 W for both simulation and load-pull measurements. 

Fig: Two-finger GaN-HEMT: a) layout; b) equivalent SPICE subcircuit

Acknowledgement: The research reported in this work has been supported by ADD (Agency of Defense Development) of Korea under an R&D program (UC170025FD).

Analog IC Designer's Handbook

Top-Down method at work in analog IC design

by Jean-Francois Debroux

 

Abstract: Analog IC design is one of the particular design activities where designers get feedback on their choices only months after they finish their design and where the cost of even the smallest design change is huge.

This has historically brought the need for new tools such as SPICE, the ancestor of almost all the electric simulators, so as to give feedback on the design choices before actually getting the prototypes. This should also have deeply impacted the design methods, and it has, but the availability of simulators has finally allowed the old “try and fix” method not only to survive but also to stay very popular.

If tools such as electric simulators have gained popularity in most electronic design fields, even out of the IC design world, methods such as the TOP-DOWN approach are not as popular as they should be, especially in the analog design community, even in the analog IC design microcosm. This is probably because this method is felt as difficult to use practically even though most designers agree that it is the right approach.

The goal of this book is to show that the TOP-DOWN approach for analog design is not only valid but that it is one of the most powerful available methods to create good analog design without sacrificing the time to market. This method creates faster and better designs but requires a good understanding of the method itself, of course, but also of the underlying techniques and of the basic design elements.

After a general introduction of the TOP-DOWN method goals and principles in the first part, the second part presents and details analog IC design elements from components to basic building blocks with a strong emphasis on practical aspects. Various additional design techniques are then detailed in the third part. The reader is then ready for the main course, a series of design examples based on the TOP-DOWN method that are grouped in the fourth part. These examples are processed the way they are in real life, from specification to implementation, from general considerations down to implementation details. Analysis of existing circuits is useful for learning but real life design is synthesis, not analysis.

Finally, the fifth part introduces or reminds useful basic concepts and presents the notation in use through the book.

The methods and techniques described in this book have been used by the author through 25 years of analog and mixed signal ICs design experience in various application fields including RF and sensor signal conditioning for various markets such as industrial, automotive and aerospace. The author feels that the method he presents in this book can help many analog electronic designers in their day to day work and hopes it will bring both a deeper understanding of design and a broader view over design activities. [read more...]

Contact / Feedback: jean-francois.debroux@orange.fr

Experience: See  Jean-Francois Debroux profile on LinkedIn

Leti Workshop at SISPAD 2019

Leti is pleased to invite you to attend our ‘Advanced Simulations for Emerging Non-Volatile Memory Technologies’ seminar, which is organized as an official satellite event of the 2019 IEEE SISPAD Conference (http://www.sispad2019.org). By the proposed seminar, we will emphasize how simulation and modeling support memory technology developments and device behavior understanding.

This event will held on Tuesday, September 3rd from 5:00 PM to 7:30 PM, Palazzo di Toppo Wassermann, Università degli Studi di Udine, Udine, Italy (i.e. at the SISPAD 2019 conference location).

PROGRAM

• Welcome and Introduction – T. Poiroux
• Innovative non-volatile memory technologies: a revolution for the storage towards a memory that thinks – G. Navarro
• Electro-thermal and material simulations for PCM – O. Cueto
• Multiphase field method for the simulation of the complex phase changes in PCM – R. Bayle
• Invited talk: Self-consistent TCAD simulation of chemical reactions within electronic devices. Application to CBRAM and OxRAM – Silvaco
• Networking cocktail

Registration is free but, due to limited seats, please register just sending an email to thierry.poiroux@cea.fr and sebastien.martinie@cea.fr.

Feel free to share this invite with your colleagues !

Digital and analog TFET circuits: Design and benchmark

Solid-State Electronics
Volume 146, August 2018, Pages 50–65
Invited Review

S. Strangio^a,b, F. Settino^a,b, P. Palestri^a, M. Lanuzza^b, F. Crupi^b, D. Esseni^a, L. Selmi^a,c

^aDPIA, Università degli Studi di Udine, Via delle Scienze 206, I-33100 Udine, UD, Italy
^bDIMES, Università della Calabria, Via P. Bucci, 41C, I-87036 Arcavacata di Rende (CS), Italy
^cDipartimento di Ingegneria “Enzo Ferrari”, Università degli Studi di Modena e Reggio Emilia, I-41100 Modena, Italy

ARTICLE INFO: The review of this paper was arranged by Prof. S. Cristoloveanu
https://doi.org/10.1016/j.sse.2018.05.003

HIGHLIGHTS:

• We report simulations of basic analog and digital circuit blocks employing tunnel-FETs.
• Template III-V heterojunction tunnel-FETs are benchmarked against silicon FinFETs for the 10 nm node.
• Performance are evaluated down to VDD = 200 mV.
• Tunnel-FETs result advantageous with respect to silicon FinFET for VDD below approximately 400 mV.

ABSTRACT: In this work, we investigate by means of simulations the performance of basic digital, analog, and mixed-signal circuits employing tunnel-FETs (TFETs). The analysis reviews and complements our previous papers on these topics. By considering the same devices for all the analysis, we are able to draw consistent conclusions for a wide variety of circuits. A virtual complementary TFET technology consisting of III-V heterojunction nanowires is considered. Technology Computer Aided Design (TCAD) models are calibrated against the results of advanced full-quantum simulation tools and then used to generate look-up-tables suited for circuit simulations. The virtual complementary TFET technology is benchmarked against predictive technology models (PTM) of complementary silicon FinFETs for the 10nm node over a wide range of supply voltages (VDD) in the sub-threshold voltage domain considering the same footprint between the vertical TFETs and the lateral FinFETs and the same static power. In spite of the asymmetry between p- and n-type transistors, the results show clear advantages of TFET technology over FinFET for VDD lower than 0.4V. Moreover, we highlight how differences in the I-V characteristics of FinFETs and TFETs suggest to adapt the circuit topologies used to implement basic digital and analog blocks with respect to the most common CMOS solutions.

FIG: Sketch of n- and p-type TFET and FinFET device architectures. The red and blue colors indicate the n- and p-doping types, respectively (green: intrinsic semiconductor, transparent-grey: oxide). TFET dimensions are: LG=20nm, nanowire cross section (LS)=7nm, EOT=1nm. FinFET dimensions are: LG=14nm, tfin=8nm, hfin=21nm, EOT=0.88nm. (For interpretation of the references to colour in this figure legend, the reader is referred to the web version of this article.)

ICNF 2017: 2nd Call for Papers

24th International Conference on Noise and Fluctuations (ICNF 2017) 

20-23 of June 2017 in Vilnius, Lithuania

We would like to invite you to submit your abstracts. For submission of the abstracts, please, REGISTER and go to the Abstract submission site. Instruction for authors and templates for abstract preparation can be found and downloaded  at the Conference website: http://www.icnf2017.ff.vu.lt/paper-submission/instructions-for-authors
Deadline of the abstract submission is 22 January, 2017

Please also keep in mind ICNF2017 important dates:

• Abstract submission deadline: 22 January, 2017
• Notification of acceptance deadline: 27 February, 2017
• Full paper submission deadline:27 March, 2017
• Early bird registration: 19 April, 2017
• Conference: 20-23 June, 2017

Please share this information to your colleagues and those who might be interested in ICNF 2017.

For more information visit the Conference website: http://www.icnf2017.ff.vu.lt/
or contact us: icnf2017@ff.vu.lt

Looking forward to meeting you in Vilnius.

With best regards,
Sandra Pralgauskaitė and Paulius Sakalas - Organizing Committee Chairs

Simulating the World’s Smallest Integrated Switch

This visualization from CSCS in Switzerland shows the world’s smallest integrated switch.

The switch is based on the voltage-induced displacement of one or more silver atoms in the narrow gap between a silver and a platinum plate.

Researchers working under Juerg Leuthold, Professor of Photonics and Communications at ETH Zurich, have created the world’s smallest integrated optical switch. Applying a small voltage causes an atom to relocate, turning the switch on or off. ETH Professor Mathieu Luisier, who participated in this study, simulated the system using Piz Daint Supercomputer. The component operates at the level of individual atoms. The team’s latest development was recently presented in the journal Nano Letters.