[workshop] Advances in Semiconductor and Emerging Devices for Chip Design

5-Day Online International Workshop on

Recent Advances in Semiconductor and Emerging Devices for Chip Design

Oct. 6-10, 2025

Organized by the Department of Electronics, Dhanamanjuri University (DMU), Manipur,

in Collaboration with IEEE Silchar Subsection

Upcoming 5-Day International Workshop on “Recent Advances in Semiconductor and Emerging Devices for Chip Design” (6–10 October 2025) organized by Dhanamanjuri University (DMU) Manipur, in collaboration with IEEE Silchar Section. This unique event, led by Dr. Khoirom Johnson Singh, Ph.D. and his dedicated team, brings together global experts from India, Europe, and beyond. Register Online

With speakers covering topics from GaN devices and memristors to cryogenic CMOS, nanosheet FETs, biomedical circuits, and spintronics for novel computing, this workshop will serve as a melting pot of ideas, a platform for young researchers and students to learn, question, and seed new collaborations.

Education equips young minds with the foundations of knowledge, preparing them to understand technological advancements and their role in shaping society. Yet, in research, knowledge alone is not enough. To truly innovate, we must disseminate our work, engage with peers, and foster collaborations across disciplines and borders. This is where the seeds of research truly take root and grow.

Collaboration is more than sharing data or co-authoring papers. It is about bringing together diverse perspectives, connecting physics with engineering, theory with experimentation, and academia with industry. Interdisciplinary approaches not only accelerate breakthroughs, but also open new directions that no single researcher could achieve alone.

Register Online...

Recent Compact Modeling Papers

[1] Hao Su, Yunfeng Xie, Yuhuan Lin, Haihan Wu, Wenxin Li, Zhizhao Ma, Yiyuan Cai, Xu Si, Shenghua Zhou Guangchong Hu, Yu He Feichi Zhou, Xiaoguang Liu, Longyang Lin, Yida Li, Hongyu Yu, and Kai Chen; "Characterizations and Framework Modeling of Bulk MOSFET Threshold Voltage Based on a Physical Charge-Based Model Down to 4 K." In 2024 IEEE European Solid-State Electronics Research Conference (ESSERC), pp. 733-736. IEEE, 2024. doi: 10.1109/ESSERC62670.2024.10719583

[2] Tung, Chien-Ting, Sayeef Salahuddin, and Chenming Hu; "A SPICE-Compatible Neural Network Compact Model for Efficient IC Simulations." In 2024 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), pp. 01-04. IEEE, 2024.

[3] Jana, Koustav, Shuhan Liu, Kasidit Toprasertpong, Qi Jiang, Sumaiya Wahid, Jimin Kang, Jian Chen, Eric Pop, and H-S. Philip Wong; "Modeling and Understanding Threshold Voltage and Subthreshold Swing in Ultrathin Channel Oxide Semiconductor Transistors." In 2024 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), pp. 01-04. IEEE, 2024.

[4] Manganaro, Gabriele. "Rethinking mixed-signal IC design." In 2024 IEEE European Solid-State Electronics Research Conference (ESSERC), pp. 552-556. IEEE, 2024

[5] Wager, John F., Jung Bae Kim, Daniel Severin, Zero Hung, Dong Kil Yim, Soo Young Choi, and Marcus Bender; "Dual-Layer Thin-Film Transistor Analysis and Design." IEEE Open Journal on Immersive Displays (2024).

[paper] Cryogenic Devices for Quantum Technologies

Jorge Pérez-Bailón, Miguel Tarancón, Santiago Celma, and Carlos Sánchez-Azqueta

Cryogenic Measurement of CMOS Devices for Quantum Technologies

IEEE Transactions on Instrumentation and Measurement (2023)

Quantum Materials and Devices (Q-MAD) Group

Institute of Nanoscience and Materials of Aragón (INMA),

Group of Electronic Design (GDE), University of Zaragoza (SP)

Abstract: In this article we present the experimental characterization of active components of a standard 65nm CMOS technology for a temperature range from 313 to 5K, analyzing the variation of the main parameters over temperature and voltage, recovering their main parameters (threshold voltage Vth, transconductance Gm and channel conductance GDS). The measurement has been carried out wire-bonding the bare dies with the devices to a dedicated printed circuit board (PCB) that has been placed inside a dilution refrigerator. The ID-VDS curves for both NMOS and PMOS transistors shows an increase of ID in the cryogenic regime that is more relevant for high values of VGS because for lower values it is partially compensated by the variation of Vth. Also, a kink is observed in these curves for high VDS values, caused by the bulk current generated by impact ionization at the drain combined with the increased resistivity of the frozen-out substrate. The transconductance Gm reaches non-zero values for higher VGS as T decreases, and then peaks to higher values in the cryogenic regime. In turn, GDS increases for increasing T, following the behavior observed for ID. Both results are in accordance with other thermal characterizations carried out on CMOS transistors in different technologies.

Fig: Detail of the IC in the measurement setup to fit into the cryostat

Aknowlegemetns: This work was supported in part by the Spanish Ministry of Science and Innovation under Grant PID2020-114110RA-I00; and in part by the CSIC Program for the Spanish Recovery, Transformation and Resilience Plan funded by the Recovery and Resilience Facility of the European Union, established by the Regulation (EU) 2020/2094 under Grant 20219PT007

[paper] Characterization and Modeling of SOI LBJTs at 4K

Yuanke Zhang, Yuefeng Chen, Yifang Zhang, Jun Xu, Chao Luo, and Guoping Guo

Characterization and Modeling of Silicon-on-Insulator 

Lateral Bipolar Junction Transistors at Liquid Helium Temperature

IEEE TED Vol. XX, No. XX, preprint arXiv:2309.09257 (2023).

University of Science and Technology of China (USTC), Hefei 230026, Anhui, China

CAS Key Lab ofQuantum Information, Hefei 230026, Anhui, China.

Abstract: Conventional silicon bipolars are not suitable for low-temperature operation due to the deterioration of current gain (β). In this paper, we characterize lateral bipolar junction transistors (LBJTs) fabricated on silicon-on insulator (SOI) wafers down to liquid helium temperature (4 K). The positive SOI substrate bias could greatly increase the collector current and have a negligible effect on the base current, which significantly alleviates β degradation at low temperatures. We present a physical-based compact LBJT model for 4 K simulation, in which the collector current (IC) consists of the tunneling current and the additional current component near the buried oxide (BOX)/silicon interface caused by the substrate modulation effect. This model is able to fit the Gummel characteristics of LBJTs very well and has promising applications in amplifier circuits simulation for silicon-based qubits signals.

Fig: IC (solid lines) and IB (dash lines) versus VBE of LBJT at different temperatures 

under (a) VBOX = 0 V; (b) VBOX = 12 V, VCE = 1 V.

Acknowledgement: The device fabrication was done by Prof. Zhen Zhang’s group in the Angstrom Microstructure Laboratory (MSL) at Uppsala University. Dr. Qitao Hu, Dr. Si Chen, Prof. Zhen Zhang are acknowledged for the device design and fabrication, and the technical staff of MSL are acknowledged for their process support.

[paper] FDSOI Threshold Voltage Model

Hung-Chi Han1, (Student, IEEE), Zhixing Zhao2, Steffen Lehmann2,

Edoardo Charbon1, (Fellow, IEEE), and Christian Enz1 (Life Fellow, IEEE)

Novel Approach to FDSOI Threshold Voltage Model Validated at Cryogenic Temperatures

in IEEE Access, DOI: 10.1109/ACCESS.2023.3283298

1 Ecole Polytechnique Fédérale de Lausanne (EPFL), 2000 Neuchâtel, Switzerland
2 GlobalFoundries, 01109 Dresden, Germany

Abstract: The paper presents a novel approach to to the modeling of the back-gate dependence of the threshold voltage of Fully Depleted Silicon-On-Insulator (FDSOI) MOSFETs down to cryogenic temperatures by using slope factors with a gate coupling effect. The FDSOI technology is well-known for its capability to modulate the threshold voltage efficiently by the back-gate voltage. The proposed model analytically demonstrates the threshold voltage as a function of the back-gate voltage without the pre-defined threshold condition, and it requires only a calibration point, i.e., a threshold voltage with the corresponding back-gate voltage, front- and back-gate slope factors, and work functions of front and back gates. The model has been validated over a wide range of the back-gate voltages at room temperature and down to 3 K. It is suitable for optimizing low-power circuits at cryogenic temperatures for quantum computing applications

FIG: Room temperature back-gate coefficient η versus VT−VB for an n-type conventional well (RVT) FDSOI FET with 1 µm of gate length and width. The θ=0 happens at VT−VB = −0.63V due to −0.63V of the front-back gate work function difference 

Acknowledgment: The authors would like to thank Claudia Kretzschmar from GlobalFoundries Germany and GlobalFoundries University Partnership Program for providing 22 FDX® test structures and support. Hung-Chi Han would like to thank Davide Braga from Fermi National Accelerator Laboratory for his valuable support. This project has received funding from the European Union’s Horizon 2020 Research & Innovation Program under grant agreement No. 871764. SEQUENCE.

[paper] Schottky Barrier FET at Deep Cryogenic Temperatures

Christian Roemer^1,2, Nadine Dersch¹, Ghader Darbandy¹, Mike Schwarz¹,

Yi Han³, Qing-Tai Zhao³, Benjamın Iniguez² and Alexander Kloes¹

Compact Modeling of Schottky Barrier Field-Effect Transistors 

at Deep Cryogenic Temperatures

EUROSOI-ULIS 2023

in Tarragona (Catalonia, Spain) on May 10-12 2023

1 NanoP, TH Mittelhessen - University of Applied Sciences, Giessen, Germany
2 DEEEA, Universitat Rovira i Virgili, Tarragona, Spain
3 Peter-Grunberg-Institute (PGI 9), Forschungszentrum Julich, Germany

Abstract: In this paper, a physics-based DC compact model for Schottky barrier field-effect transistors at deep cryogenic temperatures is presented. The model uses simplified tunneling equations at temperatures of ϑ ≈ 0 K in order to calculate the field emission injection current at the device’s Schottky barriers. The compact model is also compared to and verified by measurements of ultra-thin body and buried oxide SOI Schottky barrier field-effect transistors and is able to capture the signature of resonant tunneling effects in the transfer characteristics.

FIG: Band diagram at the source side Schottky junction (left-hand side). The solid blue line is the conduction band of the channel and the blue dashed line shows the metal’s Fermi energy level. The right-hand side subplot shows the tunneling probability, with the exponential part (red line) and the total probability, including the oscillations (green line).

Review of cryogenic neuromorphic hardware

Md Mazharul Islam¹, Shamiul Alam¹, Md Shafayat Hossain³, Kaushik Roy³, 

and Ahmedullah Aziz¹,

A review of cryogenic neuromorphic hardware

Journal of Applied Physics 133, no. 7 (2023): 070701

DOI: 10.1063/5.0133515

1Department of Electrical Engineering and Computer Science, University of Tennessee, Knoxville, Tennessee 37996, USA
2Department of Physics, Princeton University, Princeton, New Jersey 08544, USA
3Department of Electrical and Computer Engineering, Purdue University, West Lafayette, Indiana 47906, USA

ABSTRACT: The revolution in artificial intelligence (AI) brings up an enormous storage and data processing requirement. Large power consumption and hardware overhead have become the main challenges for building next-generation AI hardware. To mitigate this, neuromorphic computing has drawn immense attention due to its excellent capability for data processing with very low power consumption. While relentless research has been underway for years to minimize the power consumption in neuromorphic hardware, we are still a long way off from reaching the energy efficiency of the human brain. Furthermore, design complexity and process variation hinder the large-scale implementation of current neuromorphic platforms. Recently, the concept of implementing neuromorphic computing systems in cryogenic temperature has garnered intense interest thanks to their excellent speed and power metric. Several cryogenic devices can be engineered to work as neuromorphic primitives with ultra-low demand for power. Here, we comprehensively review the cryogenic neuromorphic hardware. We classify the existing cryogenic neuromorphic hardware into several hierarchical categories and sketch a comparative analysis based on key performance metrics. Our analysis concisely describes the operation of the associated circuit topology and outlines the advantages and challenges encountered by the state-of-the-art technology platforms. Finally, we provide insight to circumvent these challenges for the future progression of research.

FIG: (a) Biological neuron connected with multiple neurons through synapses. The inset shows the transportation of the neurotransmitter. (b) Electronic model of a neuromorphic system showing the integration of weighted spikes. (c) Several conventional hardware platforms. (d) Several cryogenic platforms for neuromorphic hardware. (e) Input spikes (Vin), corresponding membrane potential (Vmem), and output spike (Vout) of a leaky integrating and fire (LIF) neuron. An output spike is generated after Vmem crosses the threshold voltage (Vth). (f) Switching speed and switching energy comparison of conventional and cryogenic hardware.

[paper] Quasi-Fermi-Based Charge Transport Scheme for Device Simulation in Cryogenic

Quasi-Fermi-Based Charge Transport Scheme for Device Simulation 

in Cryogenic, Wide-Band-Gap, and High-Voltage Applications

Zlatan Stanojevic, Senior Member, IEEE, Jose Marıa Gonzalez-Medina, Member, IEEE, 

Franz Schanovsky, Member, IEEE, Markus Karner, Member, IEEE

TechRxiv. Preprint (2022) 

DOI:10.36227/techrxiv.21132637.v2 

Abstract: We present a novel approach to solving the transport problem in semiconductors. We reformulate the drift-diffusion equations in terms of the quasi-Fermi-energies as solution variables; a drastic increase in numerical stability is achieved, which permits the simulation of devices at cryogenic temperatures as well as wide-band-gap devices using double precision arithmetic, instead of extended precision arithmetic which would otherwise be required to solve these applications using regular drift-diffusion.

FIG: MOSFET transfer characteristics from 300K down to 4K simulated using FVM/SG/QFT at VDS=0.8V; despite only relying on double precision arithmetic, FVM/SG/QFT is capable of calculating contact currents down to 1e-310A.

[paper] RTN of a 28-nm Cryogenic MOSFET

HeeBong Yang, Marcel Robitaille, Xuesong Chen, Hazem Elgabra, Lan Wei, Na Young Kim

Random Telegraph Noise of a 28-nm Cryogenic MOSFET in the Coulomb Blockade Regime

IEEE Electron Device Letters, vol. 43, no. 1, pp. 5-8, Jan. 2022

DOI: 10.1109/LED.2021.3132964.

  

* Institute for Quantum Computing, Waterloo Institute for Nanotechnology (CA)

Abstract: We observe rich phenomena of two-level random telegraph noise (RTN) from a commercial bulk 28-nm p-MOSFET (PMOS) near threshold at 14 K, where a Coulomb blockade (CB) hump arises from a quantum dot (QD) formed in the channel. Minimum RTN is observed at the CB hump where the high-current RTN level dramatically switches to the low-current level. The gate-voltage dependence of the RTN amplitude and power spectral density match well with the transconductance from the DC transfer curve in the CB hump region. Our work unequivocally captures these QD transport signatures in both current and noise, revealing quantum confinement effects in commercial short-channel PMOS even at 14 K, over 100 times higher than the typical dilution refrigerator temperatures of QD experiments (< 100 mK). We envision that our reported RTN characteristics rooted from the QD and a defect trap would be more prominent for smaller technology nodes, where the quantum effect should be carefully examined in cryogenic CMOS circuit designs.

Fig: (a) The trapping behaviors are illustrated with empty trap (solid line) and occupied trap (dashed line) across the hump area of the |ID| -|VGS| sweep. (b) The current power spectral density (PSD) of the discretized data with the 1/f2 PSD guideline in red.

Acknowledgment: J. Watt and C. Chen in Intel for samples, A. Malcolm for early work, and J.Baugh for helpful discussions are appreciated.

[PhD] Cryogenic MOSFET Modeling

Cryogenic MOSFET Modeling for Large-Scale Quantum Computing

Arnout Lodewijk M BECKERS

Thèse n° 8365 2021

DOI: 10.5075/epfl-thesis-8365

Présentée le 28 mai 2021

Faculté des sciences et techniques de l’ingénieur Laboratoire de circuits intégrés Programme doctoral en génie électrique

pour l’obtention du grade de Docteur ès Sciences par

Arnout Lodewijk M BECKERS

Acceptée sur proposition du jury:

Prof. E. Charbon, président du jury
Prof. C. Enz, directeur de thèse
Prof. B. Parvais, rapporteur
Prof. G. Ghibaudo, rapporteur
Dr J.-M. Sallese, rapporteur 

Abstract: Promising results of state-of-the-art quantum computers fuel a world-wide effort in academic and private research laboratories to scale up the number of qubits and improve their characteristics in large arrays. To meet the scale-up challenge, innovative microelectronic architectures are envisioned hosting qubits and transistors in silicon. Integrated-circuit design for deep-cryogenic temperatures (below 10 K or -263.15°C) is a challenging optimization exercise that currently leads to costly iterations due to the lack of physics-based transistor models for these temperatures. Proposed enhancements to the industry-standard transistor models neglect the low-temperature physics and do not suffice for a large-volume application. This PhD thesis pushes the state-of-the-art of the characterization, physics, and modeling of CMOS (Complementary Metal Oxide Semiconductor) transistors down to deep-cryogenic temperatures. The most advanced commercial bulk CMOS technology (28-nm minimum gate length) is measured down to 4.2 K using dip-stick measurements and probe-station measurements. The temperature behavior of the physical parameters and the analog figures-of-merit is reported. A similar characterization study is presented for a 28-nm FDSOI CMOS technology using measurements provided by CEA-Léti through the EU H2020 MOS-Quito Project. It is shown that the design methodology based on the transconductance efficiency remains valid down to 4.2 K for both advanced CMOS processes. These results are already supporting the community: qubit controllers in 28-nm bulk and FDSOI technologies have been successfully deployed in the cryostats of quantum computers by Google and CEA-Léti, respectively. Industry-standard models have been honed over many years for near room-temperature operation. They show the largest discrepancies in the sub- and near-threshold regimes when used at deep-cryogenic temperatures. Therefore, this thesis presents an in-depth study of these regimes. Generalized Boltzmann relations are derived including band tails, which are valid in subthreshold. Using these relations, a new analytical theory is derived for the subthreshold swing that rolls off from the Boltzmann limit, showing that an ideal step-like switch cannot be obtained in the 0-K limit due to shallow band-edge states. The process quality must be improved to operate devices closer to the Boltzmann limit. Moreover, the transconductance efficiency in weak inversion (subthreshold) follows the new theoretical limit instead of the Boltzmann temperature limit. This mitigates the expected current savings from biasing in weak inversion. The new theory also explains the impossible inverse temperature dependence of the subthreshold-slope factor, which has been extracted in numerous characterizations in the literature. Furthermore, a threshold-voltage model for bulk CMOS is presented including dopant freezeout and interface traps. Process engineers can benefit from this model to customize transistors for use at 4.2 K. Finally, the discrepancy of the transfer characteristics in moderate inversion (near-threshold) is modeled with an improved representation of the localized band-edge states. As such, this PhD thesis lays the groundwork for next-generation deep-cryogenic IC design benefiting from physics-based knowledge. While this thesis is oriented toward quantum computing, the results also apply to other deep-cryogenic applications at the forefront of science and engineering.

Fig: Different explanations have been proposed for the deviation of the subthreshold swing (SS) from the Boltzmann limit at deep-cryogenic temperatures (below a critical temperature Tc). This led to the introduction of band-edge states to explain SS(T)

[papers] Compact Modeling

[1] Zhang, Yuanke, Tengteng Lu, Wenjie Wang, Yujing Zhang, Jun Xu, Chao Luo, and Guoping Guo. "Characterization and Modeling of Native MOSFETs Down to 4.2 K." arXiv:2104.03094 (2021).

Abstract: The extremely low threshold voltage (VTH) of native MOSFETs (VTH≈0 V @ 300 K) is conducive to the design of cryogenic circuits. Previous research on cryogenic MOSFETs mainly focused on the standard threshold voltage (SVT) and low threshold voltage (LVT) MOSFETs. In this paper, we characterize native MOSFETs within the temperature range from 300 K to 4.2 K. The cryogenic VTH increases up to ∼0.25 V (W/L = 10 µm/10 µm) and the improved subthreshold swing (SS) ≈ 14.30 mV/dec @ 4.2 K. The off-state current (IOFF) and the gate-induced drain leakage (GIDL) effect are ameliorated greatly. The step-up effect caused by the substrate charge and the transconductance peak effect caused by the energy quantization in different subbands are also discussed. Based on the EKV model, we modified the mobility calculation equations and proposed a compact model of large size native MOSFETs suitable for the range of 300 K to 4.2 K. The mobility-related parameters are extracted via a machine learning approach and the temperature dependences of the scattering mechanisms are analyzed. This work is beneficial to both the research on cryogenic MOSFETs modeling and the design of cryogenic CMOS circuits for quantum chips.

Fig: I-V curves of native MOSFETs with W/L= 10/10µm measured (symbol) and calculated (solid line) at various temperatures. (a) Acomparison of the calculation results between this model and the  EKV2.6 model at 77K and 4.2K. (b) Measurement and calculation results of  the output characteristic at 4.2 K.

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[2] Qixu Xie  Guoyong Shi; An analytical gm/ID‐based harmonic distortion prediction method for multistage operational amplifiers; Int J Circ Theor Appl. 2021; 1– 27. DOI: 10.1002/cta.3012

Abstract: An analytical stage‐based harmonic distortion (HD) analysis method for multistage operational amplifiers (Op Amps) is developed in this work. This work contributes two fundamental methods that make the analytical HD prediction possible at the circuit level. Firstly, we propose that the traditionally used first order small‐signal transistor quantities gm (transconductance) and go (output conductance) in the gm/ID design methodology for bulk complementary metal‐oxide‐semiconductor (CMOS) technology can be extended to the higher order quantities gm(k) and go(k) (k=1,2,3). With proper normalization, these quantities become neutral to the device dimensions and operation currents, hence can be precharacterized by sweeping simulations and used as lookup tables. Secondly, we further develop analytical nonlinearity expressions for a set of commonly used amplifier stages, represented as the functions of the nonlinearity parameters gm(k) and go(k) of the transistors that form a stage circuit. A combination of these two fundamental methods on hierarchical nonlinearity modeling enables us to apply the existing analytical HD estimation methods for the stage‐form macromodels to predict the circuit‐level HD behavior, overcoming the need of running repeated simulations under device resizing and rebiasing. The proposed harmonic distortion analysis method has been validated by application to real multistage amplifiers, achieving HD prediction results in excellent agreement to fully transistor‐level circuit simulation results but with substantial speedup.

Cryogenic characterization of CMOS technologies

A. Beckers, F. Jazaeri, A. Ruffino, C. Bruschini, A. Baschirotto and C. Enz

Cryogenic characterization of 28 nm bulk CMOS technology for quantum computing

47th ESSDERC, Leuven, Belgium, 2017, pp. 62-65.

Abstract: This paper presents the first experimental investigation and physical discussion of the cryogenic behavior of a commercial 28 nm bulk CMOS technology. Here we extract the fundamental physical parameters of this technology at 300,77 and 4.2 K based on DC measurement results. The extracted values are then used to demonstrate the impact of cryogenic temperatures on the essential analog design parameters. We find that the simplified charge-based EKV model can accurately predict the cryogenic behavior. This represents a main step towards the design of analog/RF circuits integrated in an advanced bulk CMOS process and operating at cryogenic temperature for quantum computing control systems [read more...] doi: 10.1109/ESSDERC.2017.8066592

R. M. Incandela, L. Song, H. A. R. Homulle, F. Sebastiano, E. Charbon and A. Vladimirescu

Nanometer CMOS characterization and compact modeling at deep-cryogenic temperatures

47th ESSDERC, Leuven, Belgium, 2017, pp. 58-61.

Abstract: The characterization of nanometer CMOS transistors of different aspect ratios at deep-cryogenic temperatures (4 K and 100 mK) is presented for two standard CMOS technologies (40 nm and 160 nm). A detailed understanding of the device physics at those temperatures was developed and captured in an augmented MOS11/PSP model. The accuracy of the proposed model is demonstrated by matching simulations and measurements for DC and time-domain at 4 K and, for the first time, at 100 mK [read more...] doi: 10.1109/ESSDERC.2017.8066591