Workshop on Advanced Integrated Circuit Design

U.S.-Japan Collaborative Workshop on Advanced Integrated Circuit Design

(Phase 2)

Fukuoka System LSI Development Center 2F

May 14 - May 15, 2024

https://www.kerc.or.jp/seminar/2024/04/5145152.html

In recent years, R&D and investment in semiconductors have become more active in countries around the world, and at the same time, the need for human resource development has been pointed out. In Japan in particular, the construction and attraction of factories for semiconductor "manufacturing" is accelerating, and various activities are being developed, but in the future, it is necessary to accelerate discussions on semiconductor "design". Against this backdrop, with the support of the U.S. Consulate in Fukuoka, we decided to hold a workshop in collaboration with the U.S. In December 2023, we held the U.S.-Japan Collaborative Workshop on Circuit Design (Phase 1), a state-of-the-art integrated circuit design, with the aim of learning about the latest situation in both countries through lectures on cutting-edge design technology and human resource development in Japan and the United States, as well as discussing the future direction and possibilities for international collaboration. We cover a wide range of topics, including open IC design, advanced analog and digital circuit design, generative AI processing (LLM) acceleration, optical circuit design, cryogenic classical and quantum computing, and new device technologies. Hybrid format (lectures can be held at Fukuoka venues and ZOOM Webinars), free of charge, with simultaneous English-Japanese interpretation. Therefore, it is a form that is easy to participate in. This is a good opportunity to learn about global trends, so not only those who specialize in semiconductors, but also those who are even a little interested in semiconductors, please join us. Students are also welcome to participate! In addition, we plan to have a simple hands-on session in the tutorial session, so if you are interested, please bring / prepare a laptop.

Outline of the event

Date & Time

DAY-1: May 14, 2024 10:00 a.m. ~ 4:00p.m.
DAY-2: May 15, 2024 10:00 a.m. ~ 4:05 p.m.

Hybrid format (lectures can be held at Fukuoka venues and ZOOM Webinars)
Online (Zoom Webinars)

Fukuoka Venue: Fukuoka System LSI Development Center 2F
(〒814-0001 3-8-33 Momochihama, Sawara-ku, Fukuoka City)
There is no parking lot at the venue, so if you come by car, please use the
nearby paid parking lot.

Participation Fee:  free

Application
[Application deadline: May 13]
Please apply from the link below (you can also apply for either Day-1 or Day-2 only). Simultaneous interpretation in English and → is available at the Fukuoka venue and ZOOM Webinars. The first 70 people to participate at the Fukuoka venue and the first 400 people to participate in the ZOOM Webinar will be closed to the first 400 people. If you wish to cancel after applying for the Fukuoka venue, please contact us as soon as possible. In addition, we are planning a simple hands-on, so please bring your laptop (you can participate without a laptop).

Application Form

Program Details  (subject to update) https://www.kerc.or.jp/seminar/2024/04/5145152.html

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Day-1: May 14, 10:00-16:00 (JST)

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10:00 - 10:05 Opening Remark and Overview of the Workshop, Mehdi Saligane/Koji Inoue, University of Michigan/Kyushu University

[Morning Session: Invited Talks]
10:05 - 10:10 Welcome Remarks from the U.S. Consulate in Fukuoka
10:10 - 10:55 LLMs on ASICs, Greg Kielian/Kauna Lei, Google Research
11:00 - 11:45 Teaching Mixed-Signal Design Using Open-Source Tools, Boris Murmann, University of Hawaii
11:45 - 13:00 Lunch Break

[Afternoon Session: Tutorials]
13:00 - 14:00 Photonic and Analog circuits with GDSFactory, Joaquin Matres/Troy Tamas, Google X/DoPlayDo, Inc.
14:00 - 14:15 Break
14:15 - 15:45 ReaLLMASIC: Build your own Lightweight LLM, Gregory Kielian/Kauna Lei/Shiwei Liu/Mehdi Saligane, Google Research/University of Michigan
15:45 - 16:00 Conclusion, Mehdi Saligane, University of Michigan

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Day-2: May 15th, 10:00-16:05 (JST) 

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10:00 - 10:05 Opening Remark and Overview of Day-2 Workshop, Mehdi Saligane/Koji Inoue, University of Michigan/Kyushu University
[Morning Session: Invited Talks]
10:05 - 10:50 Superconductor Computer Architecture: from Classical to Quantum, Ilkwon Byun, Kyushu University
10:50 - 11:35 Overview of new devices in the era of Beyond CMOS, Sadayuki Yoshitomi, Megachips
11:35 - 13:00 Lunch Break
[Afternoon Session: Tutorials]
13:00 - 13:55 (Tentative: GLayout), Anhang Li/Boris Murmann/Mehdi Saligane, University of Michigan/University of Hawaii
13:55 - 14:50 (Tentative: XLS: High-Level Synthesis), Johan Euphrosine, Google
14:50 - 15:05 Break
15:05 - 16:00 Pitfalls of Open-Source Chip Design Verification, Mitch Bailey, Efabless/ShuhariSystem
16:00 - 16:05 Conclusion and Overview of the phase-2 workshop activities, Mehdi Saligane/Koji Inoue, University of Michigan/Kyushu University

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Organizer

University of Michigan
Kyushu University System LSI Research Center Kyushu University
Quantum Computing Systems Research Center Kyushu University
Value Creation Semiconductor Human Resource Development Center

Co-organizers
Fukuoka Prefectural Foundation for the Promotion of Industry, Science and Technology Kyushu Economic Research Association

Sponsor
U.S. Consulate in Fukuoka

Inquiries
ic-design-ws 'at' slrc.kyushu-u.ac.jp (replace 'at' with @)
Okano, Business Development Department, TEL: 092-721-4907

[course] MEAD @ EPFL

Low-Power Analog Circuit Design

Live Course @ EPFL, Lausanne, Switzerland

JUNE 17-21, 2024

Registration Deadline: May 17, 2024 >> REGISTER

MONDAY, June 17
8:30 am-12:00 pm	MOS Transistor Modeling for Low-Voltage and Low-Power Circuit Design	Christian Enz
1:30-5:00 pm	Design of Low-Power Analog Circuits using the Inversion Coefficient	Christian Enz
TUESDAY, June 18
8:30 am-12:00 pm	Noise Performance of Elementary Circuit Blocks	Boris Murmann
1:30-5:00 pm	Opamp Topologies and Design Fundamentals	Boris Murmann
WEDNESDAY, June 19
8:30-10:00 am	Low-Power High Efficiency OpAmp Design	Klaas Bult
10:30 am-12:00 pm	Low-Power High Efficiency Residue Amplifiers	Klaas Bult
1:30-3:00 pm	Analog Design Methodology and Practical Techniques for Frequency Compensation	Vadim Ivanov
3:30-5:00 pm	Energy Efficient Voltage References, Biasing in Analog Systems and Current Sources	Vadim Ivanov
THURSDAY, June 20
8:30-10:00 am	Power Dissipation in ADC Buidling Blocks	Klaas Bult
10:30 am-12:00 pm	Power Dissipation in ADCs	Klaas Bult
1:30-5:00 pm	Micropower ADCs	Kofi Makinwa
FRIDAY, June 21
8:30 am-12:00 pm	Energy Efficient Sensor Interfaces	Taekwang Jang
1:30-5:00 pm	Low-Power Frequency Reference Circuits	Taekwang Jang
1:30-5:00 pm	Power Management With Nanoampere Consumption and Efficient Energy Harvesting	Vadim Ivanov

FOSS Circuit Simulators

AN OPEN-SOURCE, FREE CIRCUIT SIMULATOR

by: Bryan Cockfield on July 30, 2023

The original circuit simulation software, called the Simulation Program with Integrated Circuit Emphasis, or SPICE as it is more commonly known, was originally developed at the University of Califorina Berkeley in the 1970s with an open-source license. That’s the reason for the vast versions of SPICE available now decades after the original was released, not all of which are as open or free as we might like [1].

Fig: The Quite Universal Circuit Simulator includes a GUI based on the Qt toolkit and handles ad and ac analysis, S-parameters, harmonic balance analysis, noise analysis, and so forth. 

We’ve [2] listed all the simulators we found - the good, the bad, and the ugly - that actually did perform circuit simulation in some fashion. They are provided alphabetically, along with the most notable benefits and drawbacks we uncovered.

REF:
[1] An Open-Source, Free Circuit Simulator by Bryan Cockfield on July 30, 2023
[2] Best free analog circuit simulators by Lee Teschler on January 26, 2022

[book] Device Circuit Co-Design Issues in FETs

Device Circuit Co-Design Issues in FETs

Editors: Shubham Tayal, Billel Smaani, Shiromani Balmukund Rahi, Samir Labiod, Zeinab Ramezani

ISBN 9781032414256280 Pages 269 B/W Illustrations 

August 22, 2023 by CRC Press

Description

This book provides an overview of emerging semiconductor devices and their applications in electronic circuits, which form the foundation of electronic devices. Device Circuit Co-Design Issues in FETs provides readers with a better understanding of the ever-growing field of low-power electronic devices and their applications in the wireless, biosensing, and circuit domains. The book brings researchers and engineers from various disciplines of the VLSI domain together to tackle the emerging challenges in the field of engineering and applications of advanced low-power devices in an effort to improve the performance of these technologies. The chapters examine the challenges and scope of FinFET device circuits, 3D FETs, and advanced FET for circuit applications. The book also discusses low-power memory design, neuromorphic computing, and issues related to thermal reliability. The authors provide a good understanding of device physics and circuits, and discuss transistors based on the new channel/dielectric materials and device architectures to achieve low-power dissipation and ultra-high switching speeds to fulfill the requirements of the semiconductor industry. This book is intended for students, researchers, and professionals in the field of semiconductor devices and nanodevices, as well as those working on device-circuit co-design issues.

Table of Contents

1. Modeling for CMOS Circuit Design. 

2. Conventional CMOS Circuit Design. 

3. Compact modeling of junctionless Gate-All-Around MOSFET for circuit simulation. 

4. Novel Gate-Overlap Tunnel FETs for Superior Analog, Digital, and Ternary Logic Circuit Applications. 

5. Phase Transition Materials for Low Power Electronics. 

6. Impact of total ionizing dose effect on SOI-FinFET with spacer engineering. 

7. Scope and Challenges with Nanosheet FET based Circuit design. 

8. Scope with TFET based Circuit and System Design. 

9. An overview of FinFET based Capacitorless 1T-DRAM. 

10. Literature Review of the SRAM Circuits Design Challenges. 

11.Challenges and Future Scope of Gate-All-Around (GAA) Transistors: 

Physical Insights of Device-Circuit Interactions. 

[book] Circuit Simulation and Modeling with Phyton

Circuit Simulation and Modeling with Phyton

Hardcover – April 9, 2021

by Kenji Mori (author), Akira Matsuzawa (author)

This book is written for people who are learning Python. Circuit simulation and modeling are selected as subjects for programming using Python. The process of building a net" is attached to Chapter 5 appendix "Diode/MOSFET Coding Flow Diagram". Text Python source code suitable for learning by students and companies / corporations can be downloaded from the web.

About the Authors

Akira Matsuzawa: Professor Emeritus, Tokyo Institute of Technology President of Tech Idea Co., Ltd. 1978; Completed master's course at Graduate School of Engineering, Tohoku University. Joined Matsushita Electric Industrial (now Panasonic) in the same year 1997; Completed doctoral program at Graduate School of Engineering, Tohoku University 2003; Professor, Graduate School of Science and Engineering, Tokyo Institute of Technology 2018 Retired from Tokyo Institute of Technology Professor Emeritus at the same university

His books:
"First analog electronic circuit basic circuit edition" Kodansha (2015)
"First Analog Electronic Circuit Practical Circuit Edition" Kodansha (2016)
"Analog RFCMOS Integrated Circuits Basic Edition" Baifukan (2010)
"Analog RFCMOS Integrated Circuits Application Edition" Baifukan (2011)
"Learning Circuit Simulation and Modeling with MATLAB" Torikagesha (2020)

Kenji Mori: Part-time Lecturer, Tokyo Institute of Technology March 1979. Graduated from Tokushima University Graduate School of Electrical Engineering, joined NEC Corporation in the same year, engaged in circuit simulator development, automatic filter design program development, and circuit check program development. Joined Nippon Steel Corporation in November 1990, engaged in parameter extraction of MOSFET models. April 2009 Developed a prototype program for automatic design of mixed-signal LSI with Mr. Sugawara, an industry-academia-government collaboration researcher at Tokyo Institute of Technology. April 2014 Part-time Lecturer, Tokyo Institute of Technology

His books:
"Circuit Simulation Technology and MOSFET Modeling" Realize Riko Center (2003)
"Learning Circuit Simulation and Modeling with MATLAB" Torikagesha (2020)

[paper] Compact Modeling of Carbon Nanotube FETs

A Compact and Robust Technique for the Modeling and Parameter Extraction 

of Carbon Nanotube Field Effect Transistors

Laura Falaschetti¹, Davide Mencarelli¹, Nicola Pelagalli¹, Paolo Crippa¹, Giorgio Biagetti¹,

Claudio Turchetti¹,George Deligeorgis², and Luca Pierantoni¹

Electronics 2020, 9(12), 2199; 

DOI: 10.3390/electronics9122199

1 Department of Information Engineering, Marche Polytechnic University, 60131 Ancona, Italy
2 Microelectronics Research Group (MRG/IESL), FORTH, Greece

Abstract: Carbon nanotubes field-effect transistors (CNTFETs) have been recently studied with great interest due to the intriguing properties of the material that, in turn, lead to remarkable properties of the charge transport of the device channel. Downstream of the full-wave simulations, the construction of equivalent device models becomes the basic step for the advanced design of high-performance CNTFET-based nanoelectronics circuits and systems. In this contribution, we introduce a strategy for deriving a compact model for a CNTFET that is based on the full-wave simulation of the 3D geometry by using the finite element method, followed by the derivation of a compact circuit model and extraction of equivalent parameters. We show examples of CNTFET simulations and extract from them the fitting parameters of the model. The aim is to achieve a fully functional description in Verilog-A language and create a model library for the SPICE-like simulator environment, in order to be used by IC designers.

Figure 2. 3D structure of CNTFET. Reprinted, with permission, from [I and II]

Aknowlwgement: This research was supported by the European Project “NANO components for electronic SMART wireless circuits and systems (NANOSMART)”, H2020—ICT-07-2018-RIA, n. 825430.

References:

[I] Deng, J.; Wong, H.P. A Compact SPICE Model for Carbon-Nanotube Field-Effect Transistors Including non-idealities and Its Application—Part I: Model of the Intrinsic Channel Region. IEEE Trans. Electron Devices 2007, 54, 3186–3194

[II] Deng, J.; Wong, H.P. A Compact SPICE Model for Carbon-Nanotube Field-Effect Transistors Including non-idealities and Its Application—Part II: Full Device Model and Circuit Performance Benchmarking. IEEE Trans. Electron Devices 2007, 54, 3195–3205