[paper] Strategic Thinking on Open-Source PDK

(Medium link)

Written by Jun-ichi OKAMURA

IEEE Senior member (Bio)

In 1990, NHK hailed Japan as an "lectronic powerhouse," spotlighting the semiconductor industry. Now, three decades later, the spotlight has swung back onto semiconductors - though the star this time is cutting-edge manufacturing technology. In this piece, however, The Author’d like to shift the focus to the design side of semiconductors. This article follows in the footsteps of several earlier posts: "The Tale of PDKs, Past and Present" posted Dec. 3, 2023; "A Qualitative Cost Analysis of the Semiconductor Business" posted Aug.1, 2024; and "Semiconductors We Want to Make, Semiconductors We Want to Use" posted Dec. 23, 2024. I’m grateful that these pieces still receive steady traffic, and The Author hopes they’ve helped broaden my understanding of the design aspects of semiconductors for those in the industry.

This time, under the title “Strategic Thinking on Open-Source PDK (Process Design Kit),” The Author aims to explain key points about open-source PDKs clearly. The discussion doesn’t stop at semiconductor designers — it also addresses perspectives relevant to foundries (semiconductor manufacturing service providers) and those planning semiconductor-related businesses. The Author hopes you’ll find it an engaging read and a helpful resource.

Note: The views expressed here are authors's own, based on past work experience, and do not represent any organization.

[paper] Rapid MOSFET Threshold Voltage Testing

Michael H. Herman; Trenton T. Nguyen; Ken Wong; Jeff Johnson; Ben Morris

Rapid MOSFET Threshold Voltage Testing

for High Throughput Semiconductor Process Monitoring

2024 IEEE 36th International Conference on Microelectronic Test Structures (ICMTS)

Edinburgh, United Kingdom, 2024, pp. 1-6

doi : 10.1109/ICMTS59902.2024.10520252

* Parametric Test Group, Advantest America, San Jose, CA 95134 United States

Abstract : We describe a method for rapid MOSFET threshold voltage (Vt) measurement. Multiple spot Ids measurements are compared to stored reference data. Each spot measurement yields an independent Vt estimate, and these enable quality metric calculation. A Vt and quality metric can be measured within 7 msec, using two spot measurements. The method permits parallel MOS testing.

FIG : Reference Ids-Vgs Curve with Gm curveB2Q8 device 2N7002 NMOS Transistor
at Vds = 0.05 Gm(max) 0.02272 at Vgs 2.25V; Extrap tangent line at 1.8665V

[C4P] MIXDES 2024

The MIXDES conference series started in Dębe near Warsaw in 1994 and has been organized yearly in the most interesting Polish cities. In 2024 we would like to continue the tradition of inviting you to the most attractive places in Poland and the conference will take place in Gdańsk between June 27-29, 2024

In short period of time the conference has become an important event in the Central Europe allowing to discuss the recent research progress in the field of design, modelling, simulation, testing and manufacturing in various areas such as micro- and nanoelectronics, semiconductors, sensors, actuators and power devices as well as their interdisciplinary applications.

The topics of the MIXDES 2024 Conference include:

• Design of Integrated Circuits and Microsystems
  Design methodologies. Digital and analog synthesis. Hardware-software co-design. Reconfigurable hardware. Hardware description languages. Intellectual property-based design. Design reuse.
• Thermal Issues in Microelectronics
  Thermal and electro-thermal modelling, simulation methods and tools. Thermal mapping. Thermal protection circuits. 
• Analysis and Modelling of ICs and Microsystems
  Simulation methods and algorithms. Behavioral modelling with VHDL-AMS and other advanced modelling languages. Microsystems modelling. Model reduction. Parameter identification.
• Microelectronics Technology and Packaging
  New microelectronic technologies. Packaging. Sensors and actuators.
• Testing and Reliability
  Design for testability and manufacturability. Measurement instruments and techniques. 
• Power Electronics
  Design, manufacturing, and simulation of power semiconductor devices. Hybrid and monolithic Smart Power circuits. Power integration.
• Signal Processing
  Digital and analogue filters, telecommunication circuits. Neural networks. Artificial intelligence. Fuzzy logic. Low voltage and low power solutions.
• Embedded Systems
  Design, verification and applications.
• Medical Applications
  Medical and biotechnology applications. Biometrics. Thermography in medicine

Call for Papers and Contributions

A call is made for papers, contributions and other conference activities on the topics mentioned above. Full papers should be submitted till March 1, 2024 - only in electronic form (MS Word, RTF, Open Office Writer, LaTeX, together with a generated PDF file).

The paper submission form and required format is available on our Web page. Authors are asked to indicate the topic into which their papers fall. The papers will be reviewed by at least two referees from the International Programme Committee. The papers will be published in the proceedings from the author's electronic submission.

Tutorials and Special Sessions - Call for Proposals

Several tutorials/special sessions will be held prior to the conference. Authors willing to propose a tutorial at MIXDES 2024 are invited to send a proposal to the Organizing Committee. The proposal should consist of a three-page summary including tutorial title, name and affiliation of the lecturer(s), tutorial objectives and audience, topical outline and provisional schedule of the tutorial.

MINIMAL

"Minimal Fab Promotion Organization" (MINIMAL) aim is to establish a completely new production method called this minimal fab and initiating a process revolution in Japan. The mission is to further expand the application fields of Minimal Fab as the only organization in the world to support the spread and development of high-mix low-volume of microdevices such as semiconductors and MEMS as innovative industrial systems. We are aiming to become an innovation platform to promote small businesses using the Minimal Fab through collaboration among various industries such as various toolmakers, materials, parts and device users [ read more...]

Postdoc position in GaN power devices

The POWERlab (https://powerlab.epfl.ch) at EPFL is looking for excellent and motivated candidates to work on new concepts for power electronic devices based on GaN heterostructures. The candidate will pursue novel ideas related to concepts developed in our laboratory, for example [1]. The candidate will have the opportunity to work on several aspects involved in demonstrating high-performance power devices (cleanroom fabrication, device simulation and characterization) relying on the excellent facilities in our laboratory and at EPFL. Most importantly, the candidate is encouraged to try new ideas and approaches.

Profile: The candidate is expected to have a solid theoretical background in semiconductors and experience in cleanroom fabrication of GaN electronic devices, with strong aptitude to perform experiments, explore new concepts, and communicate his/her findings in high-quality scientific publications.

What is offered: The selected candidate will be offered a fellowship with very competitive salary and excellent conditions to excel in his/her research.

How to apply: If you are interested, and have the correct profile for this position, please send your CV to elison.matioli@epfl.ch, including publication list and names of two references.

REF:

[1] L. Nela, J. Ma, C. Erine, P. Xiang, T.-H. Shen, V. Tileli, T. Wang, K. Cheng and E. Matioli, “Multi-channel nanowire devices for efficient power conversion” Nature Electronics, 4, 284–290, (2021)

Commemorative and Networking Event: 75th anniversary of the transistor

IEEE Switzerland Solid State Circuits Chapter

invites you to join the networking event to celebrate

the 75th anniversary of the transistor

Three IEEE Distinguished Lecturers will talk about the transistor history and its properties. It will be followed by short presentations about semiconductor industry activities in Switzerland, with the following networking apéro.

Attendance is free and open to all: mention it and forward to your friends and colleagues.

Please register for logistics reasons. 

Date and Time	Location
Date: 30 Mar 2023 Time: 01:00 PM to 07:30 PM All times are (UTC+01:00) Bern Add Event to Calendar iCal Google Calendar	EPFL Microcity Rue de la Maladière 71C CH-2020 Neuchâtel Room Number: MC A1 272 Click here for Map

Agenda

13:00 – 13:30 Welcome Coffee 

13:30 – 14:15 Tom Lee: From Rocks to Chips: Stories of the Transistor

14:15 – 15:15 Chris Mangelsdorf: Don't try this with CMOS

15:15 – 15:45 Coffee break 

15:45 – 16:30 Christian Enz: The Design of Low-power Analog CMOS Circuits Using the Inversion Coefficient

16:30 – 17:30 Semiconductor industry in Switzerland, sharing experiences 
                        (W.Grabinski, Panel Moderator):

• Bipolar transistor manufacturing in Switzerland – Hugo Wyss
• Integrated Circuits – Eric Vittoz
• Semiconductor design in the 21st century – Alain-Serge Poret
• Micro-electronics for Swiss made products – Evert Dijkstra
• Semiconductor manufacturing equipment – André Gerde

17:30 – 19:00 Apéro riche

Hosts

Switzerland Section Chapter, SSC37 : https://sscs.ieee.ch
Switzerland Section : https://ieee.ch/

[paper] p-Type Doped Silicene-based

Mu Wen Chuan, Munawar Agus Riyadi, Afiq Hamzah, Nurul Ezaila Alias, Suhana Mohamed Sultan, Cheng Siong Lim, Michael Loong Peng Tan

Device performances analysis of p-type doped silicene-based field effect transistor using SPICE-compatible model

PLoS ONE 17(3): e0264483.: March 3, 2022

DOI: 10.1371/journal.pone.0264483

   
Universiti Teknologi Malaysia, Skudai, Johor, Malaysia
Diponegoro University, Semarang, Indonesia

Abstract: Moore’s Law is approaching its end as transistors are scaled down to tens or few atoms per device, researchers are actively seeking for alternative approaches to leverage more-than-Moore nanoelectronics. Substituting the channel material of a field-effect transistors (FET) with silicene is foreseen as a viable approach for future transistor applications. In this study, we proposed a SPICE-compatible model for p-type (Aluminium) uniformly doped silicene FET for digital switching applications. The performance of the proposed device is benchmarked with various low-dimensional FETs in terms of their on-to-off current ratio, subthreshold swing and drain-induced barrier lowering. The results show that the proposed p-type silicene FET is comparable to most of the selected low-dimensional FET models. With its decent performance, the proposed SPICE-compatible model should be extended to the circuit-level simulation and beyond in future work.

Fig: Schematic diagrams of AlSi3 FET: (a) the structure and 

(b) the ToB nanotransistor circuit model. 

Acknowledgements: 1.) Michael Tan Loong Peng - Ministry of Higher Education (MOHE) of Malaysia through the Fundamental Research Grant Scheme(FRGS/1/2021/ STG07/ UTM/02/3); The funders had no role in study design, data collection and analysis, decision to publish, or preparation of the manuscript. 2.) Munawar Agus Riyadi - World Class Research Universitas Diponegoro (WCRU) 2021 Grant no. 118-16/UN7.6.1/PP/2021; The funders had no role in study design, data collection and analysis, decision to publish, or preparation of the manuscript.

[C4P] ISPS 2021 Prague, August 25–27, 2021

 15th INTERNATIONAL SEMINAR ON POWER SEMICONDUCTORS

ISPS 2021

Prague, 25 August – 27 August 2021

---

Organised by	IET Czech Network in co-operation with the IEEE Czechoslovakia Section
Co-sponsored by	Faculty of Electrical Engineering, Department of Electrotechnology, Czech Technical University in Prague
Technical sponsor	ECPE European Center for Power Electronics e.V.
Conference website	http://technology.fel.cvut.cz/ISPS2021

BACKGROUND

The 15th International Seminar on Power Semiconductors (ISPS 2021) provides a forum for technical discussion in the area of power semiconductor devices and their applications. It is a small conference with the special flair of an atmosphere of searching deeper insight and intensive discussion.

AREAS OF INTEREST

• Power semiconductor devices (materials, physics, modelling, technology, diagnostics)
• Packaging, advanced device applications, reliability

Papers oriented in the field of power semiconductors are supposed to be presented in sessions on

• Device Physics and Technology
• Power Bipolar Devices
• Voltage-Controlled Power Devices
• Wide Bandgap Power Devices
• Power Integration
• Advanced Applications
• Packaging, Reliability & Modelling.

A round table discussion oriented on topical problems of research and education in the field of power semiconductors will be organised in the framework of the seminar.

PAPER SUBMISSION

A summary of 300–500 words (maximum two pages including figures and tables) is required for review. It should be uploaded in electronic format (.doc or .pdf files) to the ISPS 2021 easychair conference system:

http://easychair.org/conferences/?conf=isps2021

before April 30, 2021.

PUBLICATION

Presented papers will be published in the seminar proceedings, which will be distributed at the seminar registration. We are delighted to announce that the best papers presented at the conference will be invited for consideration in a special issue of the IET Power Electronics Journal dedicated to the ISPS 2021 seminar.

ORGANISING COMMITTEE

Chairman:	Prof Vítězslav Benda, FIET
Members:	Dr Vítězslav Jeřábek, MIET
	Dr Martin Molhanec
	Dr Ladislava Černá, MIET
	Dr Pavel Hrzina

[paper] Organic semiconductor (OSC) OFETs

Boyu Peng, Ke Cao* Albert Ho Yuen Lau, Ming Chen, Yang Lu* and Paddy K. L. Chan

Crystallized Monolayer Semiconductor for Ohmic Contact Resistance, High Intrinsic Gain, and High Current Density

Adv. Mater. 2020, 32, 2002281 

DOI:10.1002/adma.202002281

Department of Mechanical Engineering, The University of Hong Kong, Pokfulam Road (HK)

*Department of Mechanical Engineering, City University of Hong Kong, Kowloon (HK)

Abstract: The contact resistance limits the downscaling and operating range of organic field-effect transistors (OFETs). Access resistance through multilayers of molecules and the nonideal metal/semiconductor interface are two major bottlenecks preventing the lowering of the contact resistance. In this work, monolayer (1L) organic crystals and nondestructive electrodes are utilized to overcome the abovementioned challenges. High intrinsic mobility of 12.5 cm2 V−1 s−1 and Ohmic contact resistance of 40 Ω cm are achieved. Unlike the thermionic emission in common Schottky contacts, the carriers are pre- dominantly injected by field emission. The 1L-OFETs can operate linearly from VDS = −1 V to VDS as small as −0.1 mV. Thanks to the good pinch-off behavior brought by the monolayer semiconductor, the 1L-OFETs show high intrinsic gain at the saturation regime. At a high bias load, a maximum current density of 4.2 µA µm−1 is achieved by the only molecular layer as the active channel, with a current saturation effect being observed. In addition to the low contact resistance and high-resolution lithography, it is suggested that the thermal management of high-mobility OFETs will be the next major challenge in achieving high-speed densely integrated flexible electronics.

Fig: a) Schematic charge accumulation and b) output curves of short-channel OFETs. c) Schematic charge accumulation and d) output curves of source-gated transistors. e) Schematic charge accumulation and f) output curves of 1L-OFETs. 

Acknowledgements: The authors gratefully acknowledge the support from the General Research Fund (GRF) under Grant Nos. HKU 17264016 and HKU 17204517, University of Hong Kong Seed Funding Grant Nos. 201711159068 and 201611159208. The authors appreciate Prof. Xin Cheng and Xin Zhuang from Southern University of Science and Technology for their support on e-beam lithography. The authors also thank Dr. Hagen Klauk and James W. Borchert for the fruitful discussions and suggestions.

The ITRS, 2013 Edition is now online.

 The link below will take you to the site for the summary information
http://www.itrs.net/Links/2013ITRS/Summary2013.htm

 For the full edition details, follow this link
http://www.itrs.net/Links/2013ITRS/Home2013.htm

[read more...]