APCI Program: SBMicro Projects

APCI Program

Support for SBMicro Integrated Circuit Projects

TAB: Universities Involved in IC Design and EDA/CAD Tool Development

University	#Profs	#PhDs	#MSCs
CEFET-MG - Centro Federal de Educação Tecnológica de Minas Gerais	8	0	3
CEFET-RJ - Federal Center for Technological Education Celso Suckow da Fonseca	2	1	0
FEI - Centro Universitário da FEI	2	0	3
FURG - Universidade Federal do Rio Grande	3	1	1
IFSP - Instituto Federal de São Paulo	5	0	0
ITA - Instituto Tecnológico de Aeronáutica	10	0	5
PUCRS - Pontifícia Universidade Católica do Rio Grande Do Sul	8	15	9
UCPEL - Universidade Católica de Pelotas	3	0	6
UEA - Universidade do Estado do Amazonas	1	0	0
UERGS - State University of Rio Grande do Sul	5	0	0
UFABC - Federal University of ABC	6	0	2
UFAM - Universidade Federal de Manaus	4	4	0
UFBA - Universidade Federal da Bahia	5	13	8
UFC - Universidade Federal do Ceará	3	5	3
UFERSA - Mossoró	1	0	4
UFERSA - Pau dos Ferros	5	1	3
UFG - Federal University of Goiás	8	1	0
UFMG - Universidade Federal de Minas Gerais	6	3	9
UFPB - Universidade Federal da Paraíba	1	1	2
UFPEL - Universidade Federal de Pelotas	13	13	2
UFPR - Universidade Federal do Paraná	7	2	5
UFRGS - Universidade Federal do Rio Grande do Sul	17	32	45
UFRJ - Federal University of Rio de Janeiro	6	2	4
UFRN - Federal University of Rio Grande do Norte	4	3	2
UFS - Universidade Federal do Sergipe	3	0	1
UFSC - Universidade Federal de Santa Catarina	11	12	11
UFSM - Universidade Federal de Santa Maria	8	0	5
UFV - Universidade Federal de Viçosa	2	3	3
UNB - Universidade de Brasília	9	3	9
UNESP - Universidade Estadual Paulista	4	0	1
UNICAMP - Universidade Estadual de Campinas	8	16	21
UNIFEI - Universidade Federal de Itajubá	7	2	3
UNIFEI - Itabira	3	0	3
UNIPAMPA - Universidade Federal do Pampa	4	0	2
UNISANTOS - Universidade Católica de Santos	1	0	0
UNISINOS - Universidade do Vale do Rio dos Sinos	3	0	3
UNIVALI - Universidade do Vale do Itajaí	3	0	3
USP - Universidade de São Paulo	8	1	12
USP-EESC - Escola de Engenharia de São Carlos	3	1	2
UTFPR - Universidade Tecnológica Federal do Paraná	1	0	0

[REF] Report: Strengthening EU-Brazil bilateral know-how of semiconductor sector technologyand possibilities for cooperation on trade and R&D (July 2023)

[OpenPDK] GT2N

This the initial release for the GT2N PDK with 72 standard cells: <https://github.com/azadnaeemi/GT2N>.

It is based on 2nm GAAFET with BSPDN. All the device models are based on 3-stack nanosheets

Standard cell layouts can also be imported using the .gds file: GT2N/gds/gt2_6t_std_cells.gdsLVS and DRC rulesets for icvalidator are present in "GT2N/icv_runset".
Libraries are composed of 3 process corners (under development), 2 nanosheet width (W) flavors, and 5 threshold voltage (VT) flavors. (In the order of decreasing VT, HVT > SVT > LVT > ULVT > ELVT)

The collaterals required for synthesis and PnR are (depending on the process corner and W/VT flavor):

LIB: GT2N/lib/tt/gt2_6t_w31_lvt_tt_0p7v25c.lib
LEF: GT2N/lef/tt/gt2_6t_w31_lvt.lef
Techlef: GT2N/techlib/gt2_tech.lef
ICT: GT2N/qrc/GT2.ict
QRCTech: GT2N/qrc/GT2_qrc.tch
ITF: GT2N/nxtgrd/GT2.itf
NXTGRD: GT2N/nxtgrd/GT2.nxtgrd

The thermal-calibrated GAAFET (3-stack nanosheet) model card is (depending on the process corner and W/VT flavor):

GT2N/device/tt/gt2_w31_lvt_tt.sp

[ref] D. Jang, P. Kumar, M. N. H. Shazon, S. J. Ram, A. Svizhenko, V. Moroz, A. Ceyhan, N. A. Radhakrishn, and A. Naeemi, "GT2N: An Open-Source 2nm Nanosheet PDK Enabling Multi-Width/VT Benchmarking" in IEEE International Symposium on Circuits and Systems (ISCAS) 2026  

[ICTA2026 ] Special OpenPDK Session

IEEE International Conference on Integrated Circuits, Technologies & Applications

ICTA 2026 Special Session “OpenPDK - Global FOSS Scholar Platform"

21st - 24th (Wed - Sat) October 2026

Grand Copthorne Waterfront Hotel, Singapore

The OpenPDK initiative delivers a global FOSS Scholar Platform supporting analog/RF, mixed‑signal, and digital IC design. Central to this effort are accurate SPICE models for low‑power sensing MOSFETs, RF HBTs, and emerging RRAM devices, validated across cryogenic temperatures for space and quantum‑computing applications. The initiative also advances Verilog‑A compact‑model standardization, ensuring result reproducibility and seamless integration into open‑source design flows. Supported by the EU Chips JU, OpenPDK fosters collaboration among academia, startups, and industry, while providing FOSS IC‑design tools covering schematic capture, simulation, layout, and verification up to tape‑out. Similar to the EU Chips JU program, Zhejiang CoreXin in China offers an open‑source PDK together with tape‑out services for its 55nm CMOS process. To accelerate the semiconductor‑industry development across the Asia‑Pacific and Southeast‑Asia regions, semiconductor model development and parameter extraction techniques should be pursued in a more focused manner. This special session brings together experts to present and discuss advances in device characterization, compact modeling, simulation methodologies, and validation techniques for a broad range of solid‑state devices, including Si, III/V semiconductors, power devices, nanoscale structures, and emerging 2.5D/3D advanced packaging technologies [ read more...]

ICTA 2026 Special OpenPDK Session Presenters

• SPICE/Verilog-A standard models and OpenPDK practice
  Wladek Grabinski, GMC Consulting, Switzerland
• Open-Source Ecosystem Updates and Semiconductor Design Development Programs in Japan
  Jun-ichi Okamura, AIST Solutions, OpenSUSI, Japan
• Open-Source EDA Meets Industrial IC Design
  Ehrenfried Seebacher, ams-OSRAM AG, Austria
• Building an Open-Source Process Platform, Empowering VLSI Innovation and Development
  Da Zhang, Zhejiang University/CTO, Zhejiang Chuangxin Integrated Process Platform, China
• From Silicon to Design: Intelligent Measurement and Modeling for DTCO
  Yutao Ma, VP of R&D, Primarius Technologies. Ltd. China
• Beyond Moore, Application-Driven IC Innovation International Cooperation Opportunities at NICE
  Alex Gu, National Innovation Center Par Excellence (NICE), China
• 2.5D/3D IC: AI+EDA Reshaping the System-Design-Technology Co0ptimization (STCO) Paradigm for Advanced Packaging
  Alex Zhao, Founder/CEO Zhuhai SiChip Technology Co., Ltd., China
• Modelling of semiconductor devices: the heart of innovation bridging academia and industrial applications
  Fujiang Lin, University of Science and Technology of China (USTC), China

Special OpenPDK Session progeam include the panel discussion: 

How to have a close loop for PDK, EDA, PDA and ICS simulation?

[ read more...]

Schematic to Silicon with Mini MOSbius

Zero To ASIC Course and Tiny Tapeout by Matt Venn

Schematic to Silicon with Mini MOSbius 

https://www.youtube.com/watch?v=NM5cLWYWqG0

Take Matt Venn TT course: 

https://www.zerotoasiccourse.com/

Buy a copy of Mini MOSbius, part of the TT IP library, here: 

https://store.tinytapeout.com/products/TTSKY25b-Development-Kit-p849160072

Check the configurator: 

https://github.com/mattvenn/mini-mosbius-configurator

Mini MOSbius is available on these chips

• [OK] TTSKY25a - delivered July 2026 - available in the store
• [OK] TTSKY25b - delivered August 2026 - available in the store
• TTSKY26b - tapeout May 2026
• TTSKY26c - tapeout September 2026
• GF180 - will be taped out December 2026

and finally check out the original MOSBius: https://mosbius.org/ If you are interested to acquire MOSbius kits, review the express license and email Peter Kinget for kit availability before placing an order.

[FOSS] AI IC Designs

Harald Pretl, Kevin Cameron, Jun‑ichi Okamura

FOSS AI IC Designs Examples

Intensive work over last three months was carried out by Prof. Harald Pretl together with an AI coding agent, thru which a substantial chip‑design knowledge base was built. At this stage, the AI agent is able to design, simulate, and layout a low‑noise, low‑voltage bandgap reference plus LDO with minimal manual intervention (along with many additional circuits that will be showcased later). The rapid progress in capability development is highly impressive.

The entire implementation was performed in OpenPDK 130nm CMOS using IIC‑OSIC‑TOOLS with almost no human involvement. The resulting layout is densely packed, the floorplan is coherent, and a manually created version would not differ significantly. Dummy structures were inserted for matching, and common‑centroid placement was applied to critical MOSFET devices.

Significant progress has also been achieved by Kevin Cameron, primarily on the simulation side, covering complete digital and AMS/RF domains. The work described in the linked repository has been developed and advanced accordingly, with sv2ghdl, which translates SystemVerilog RTL into VHDL for use with GHDL and NVC simulators. The generated VHDL leverages simulator extensions that go beyond what SystemVerilog offers, including multi‑UDN wires, bidirectional components, and improved unknown‑state handling

<https://github.com/kev-cam/sv2ghdl/blob/main/README.md>

A beta version of an automatic P&R tool for the OpenPDK TR‑1um was developed by Jun‑ichi Okamura using Claude AI and FOSS KLayout API and accompanying verification scripts. The flow is based on the newly updated standard‑cell library, incorporating both LEF and Liberty files, and STA analysis is now supported. Regression testing was carried out on three designs: I²C, SPI, and TD4

<https://lnkd.in/gMy3ThYm>

The synthesis and automatic P&R of TD4, an educational 4‑bit CPU, were completed by Jun‑ichi Okamura using Claude AI and the OpenPDK TR‑1um flow. A custom 8×16 register file was designed, the standard‑cell height was reduced, and a simplified Liberty (.lib) file was created to enable static timing analysis. The final chip implementation is made up of 4225 devices.

[paper] NetlistBench: SPICE Netlist Evaluation LLM Reliability

Ma, Jiarui, Jianghan Wang, Yuheng Ma, Ziyi Zhuang, and Xiaoguang Liu

"NetlistBench: Evaluating LLM Reliability in SPICE Netlist Recognition and Manipulation" 

In Proceedings of ACM, New York, NY, 8 pages

arXiv: 2608.12197 (2026)

* Southern University of Science and Technology, School of Microelectronics Shenzhen (CN)

Abstract: Large Language Models (LLMs) are increasingly used in circuit design workflows, yet their reliability on simulator-facing SPICE netlist recognition and manipulation remains poorly understood and is rarely separated from high-level design reasoning. Although netlists are textual, they encode structured circuit objects through topology and parameters. We present NetlistBench, a structure verified benchmark for SPICE netlist recognition and manipulation. NetlistBench contains 2,342 cases across 24 task families, covering parameter and connectivity recognition and edits, hierarchical operations, equivalence judgment, and long-horizon compound editing. Model outputs are evaluated by a deterministic structure aware oracle. Across six non-thinking LLMs, performance varies substantially with operation-level structural complexity. Simple local edits reach 96%–100% accuracy, while device addition drops to 41%–83% and equivalence judgment to 49%–90%. Enabling reasoning substantially improves weaker models but does not eliminate structure-preservation failures, with performance still degrading sharply as the edit horizon increases. NetlistBench identifies netlist reliability as a distinct bottleneck for trustworthy LLM-based circuit design automation.

Fig: SPICE netlists as a common representation layer in LLM-based circuit design workflows.

[paper] SPICE-Q Quantum Chip Production

Ling Qiao Cai1,2, Bin Yang1,2, Fumin Luo1,2, Chang Liu1,2, WeiGui Guo1,2, GuoRong Zhang1,2, XueFei Liu1,2, Qinglang Guo1,2 and Bin Wu

SPICE-Q and Large-Scale Quantum Chip Production

[quant-ph] 16 Jun 2026 

arXiv:2606.17907v1  

1.) Yangtze Delta Industrial Innovation Center of Quantum Science and Technology, Suzhou, (CN)
2.) China Academy of Electronics and Information Technology, No. 11 Shuangyuan Road, Shijingshan District, Beijing, (CN)

Abstract: The historical analogy with SPICE is based on foundational reports, numerical methods, and experience from integrated circuit design. The requirements for quantum computing and scaling refer to established work in the field. The background on superconducting qubits, transmons, circuit quantum electrodynamics, microwave networks, material loss, and three‑dimensional interconnects draw from widely recognized literature. The background on parameter extraction, simulation frameworks, and manufacturability is informed by recent research and practical developments.

Table of Contents (Top‑Level Sections)

1. Abstract ... p. 4
2. The Emergence of SPICE and Large‑Scale Classical Circuits
   and Its Implications for Quantum Chips ... p. 5
3. SPICE‑Q Model Composition ... p. 24
4. SPICE‑Q Device‑Level Models ... p. 40
5. Standardized Manufacturing System ... p. 53
6. Integrating SPICE‑Q with Process Models ... p. 66
7. Design‑Technology Co‑Optimization (DTCO) ... p. 71
8. Large‑Scale Production Examples and Design Scenarios ... p. 75
9. Engineering Transition and Large‑Scale Quantum Chips ... p. 80
10. Summary ... p. 84
11. Acknowledgment ... p. 87
12. Reference ... p. 87
13. Appendix A ... p. 90

Acknowledgment The authors thank Jun Ye for helpful assistance. The authors also acknowledge the use

of AI tools for translation assistance and auxiliary text generation.

[paper] 130-nm CMOS tunnel p-bit cell

Ju-Young Yoon, Nuno Caçoilo, Advait Madhavan, Jabez J. McClelland, Shun Kanai, Hideo Ohno, Shunsuke Fukami, and William A. Borders, 

"130-nm CMOS-integrated superparamagnetic tunnel junction-based p-bit," 

in IEEE Electron Device Letters, 

DOI: 10.1109/LED.2026.3696800

Abstract: Probabilistic computers offer promising solutions for computationally hard problems in domains such as combinatorial optimization and machine learning. A key building block in these systems is the probabilistic bit (p-bit), which relies on superparamagnetic tunnel junctions (sMTJs) as its source of randomness. A challenging threshold to cross for scaling sMTJ-based p-bit systems is integration of sMTJs with CMOS technology. In this work, we present experimental results of a p-bit unit cell using sMTJs integrated with 130 nm CMOS technology and demonstrate that the sMTJ’s resistance fluctuations can generate a corresponding fluctuating digital output voltage which is tunable via the input voltage. These findings establish the feasibility of CMOS-compatible, sMTJ-based probabilistic circuits and mark a key step toward scalable hardware for real-world probabilistic computing applications. 

FIG: (a) Circuit diagram of the spintronic p-bit; b) Schematic cross-sectional structure of the spintronic p-bit. Transistors and lower interconnect layers were fabricated at SkyWater, followed by fabrication of the spintronic devices at Uni. Tohoku. (c,d) Cross-sectional and plan-view electron microscope images of the spintronic device designed to exhibit stochastic fluctuations.

Acknowledgements: This work was made possible by the NIST-led Nanotechnology Xccelerator program that distributes open-source circuit designs for integration of novel technologies on CMOS.

[FSiC2026] Open EDA · Open Silicon · Sovereign by Design

FSiC2026

Free Silicon Conference 2026

Open EDA · Open Silicon · Sovereign by Design

What is FSiC? The annual gathering of the free and open-source silicon community building open EDA tools, open PDKs, and free hardware. Three days of talks and tutorials about designing chips with software you can read, share, and modify.

Who should come? Chip designers, EDA developers, researchers, students, and anyone curious about building silicon without proprietary lock-in. All experience levels welcome.

When? 6–8 July 2026

Where? University of Ljubljana, 

Faculty of Electrical Engineering

Tržaška cesta 25

SI-1000 Ljubljana

Registration closes 22 June: https://pretix.eu/FSiC/2026/

FSiC2026 Program: https://wiki.f-si.org/index.php/FSiC2026

[Lecture 13-16] supplementary by Prof. Kim

Prof. Kwantae Kim, Analog Integrated Circuits at Aalto University, recorded additional videos that cover walkthroughs of the CAD exercises in his Integrated Analog Systems course. These videos should provide useful guidance for ADC design simulation and verification practice! 

• Integrated Analog Systems D - Lecture 13S CAD (Bootstrapped Sampling Switch)
  https://www.youtube.com/watch?v=VSDzmijax3c
• Integrated Analog Systems D - Lecture 14S CAD (Linearity and FFT)
  https://www.youtube.com/watch?v=qwJ_tlZTaq8
• Integrated Analog Systems D - Lecture 15S CAD (Transient Noise and VerilogA Modeling)
  https://www.youtube.com/watch?v=YW2nnI3DD_c
• Integrated Analog Systems D - Lecture 16S CAD (ADC ENOB Verification)
  https://www.youtube.com/watch?v=BIFXidfTYxE

Visit also webpage: https://kwantaekim.github.io

Revolution EDA Mistral AI Experiments

Revolution EDA MistralAI Experiments

by Murat Eskiyerli  

There was a recent article by Prof Razavi, where the problems of Large Language Models in identifying various analogue integrated circuit blocks were recounted.

Revolution EDA uses structured JSON data format to store design files. JSON also happens to be very easy for LLMs to parse and understand. In fact, Mistral AI has a JSON mode. Mistral AI is the latest addition to the growing number of LLMs that Revolution EDA is able to use.

We did ask a few questions to Mistral AI to test its understanding of designs in Revolution EDA and its potential to help designers. The results have been very encouraging. The future analogue integrated circuit designers will be able to use large language models like Mistral AI to quickly gain understanding of a circuit and improve on it.

The transcription below is taken exactly from the interaction with Mistral AI except for small formatting changes [read more...]

[MEAD] Low-Power Analog IC Design

MEAD Education

June 22-26, 2026

Registration deadline: May 22, 2026

Payment deadline: June 12, 2026

MONDAY, June 22
8:30-12:00 am	MOS Transistor Modeling for Low-Voltage and Low-Power Circuit Design	Christian Enz
1:30-5:00 pm	Design of Low-Power Analog Circuits using the Inversion Coefficient	Christian Enz
TUESDAY, June 23
8:30-10:00 am	Noise Performance of Elementary Circuits	Boris Murmann
10:30-12:00 am	Noise Performance of Filters, Feedback & SC Circuits	Boris Murmann
1:30-3:00 pm	Opamp Topologies and Design: Single-Stage Circuits	Boris Murmann
3:30-5:00 pm	Opamp Topologies: Cascoded and Two-Stage Circuits	Boris Murmann

[Read more and REGISTER]

[OpenSUSI] Kicks off Five-Year Plan

Industry-Academia Collaboration Project Launches for Real Chip Manufacturing 

Using NDA-Free PDK - Tokai Rika, Kyushu University, AIST Solutions, 

OpenSUSI Kicks Off Five-Year Plan for FY2026

Tokai Rika Co., Ltd., Kyushu University, AIST Solutions Co., Ltd., and OpenSUSI have announced a joint project on a five-year plan to develop semiconductor human resources and verify their implementation through industry-academia collaboration to actually manufacture chips using PDK (Process Design Kit) that does not rely on NDAs (non-disclosure agreements). The 2026 launch ceremony was held. The biggest feature of this project is that it allows students to experience a series of processes from design to chip manufacturing under an open design environment using NDA-free PDKs #OpenPDKs

Positioning and future development in FY2026 as the first year that this project will be fully developed over a five-year span. Based on an open design and manufacturing environment utilizing NDA-free PDK #OpenPDK, we will continue and develop the following initiatives:

• Continuation and advancement of hands-on semiconductor human resource development
• Providing opportunities for actual chip manufacturing and verification using NDA-free PDK
• Building a practical and highly reproducible education and implementation model through industry-academia integration
• In exchange for the cost support for this program, we will embed the company's logo on the prototype chip to spread awareness of semiconductor design human resource development as a social contribution activity

(From left) Junichi Okamura, Representative Director of OpenSUSI, 

Haruichi Kanaya, Professor of Kyushu University, 

Taketoshi Sakurai, Executive Officer of Tokai Rika, 

and Seiji Osaka, President and CEO of AIST Solutions

If you are interested or interested in this matter, please contact us at:

OpenSUSI Secretariat <secretary@opensusi.org>

 

26th Workshop Analog Circuits

26th Workshop Analog Circuits 

12.03.2026 and 13.03.2026

at Leibniz University Hannover

The workshop series offers a platform to present one's own ideas and discuss results with science and industry. The focus is on integrated analog and mixed-signal circuits.

The workshop will take place on 12.03.2026 and 13.03.2026 in the Royal Horse Stable of the University of Hannover.  Registration - Participation in the workshop is free of charge.

The programme will be compiled after the call for papers has been completed and is avalable online 

In the run-up to the 26th Workshop on Analog Circuits, the DE:Sign cooperation event on the topic of "Open Source Tools for Analog Design" will take place on the morning of 12.03.2026. In this event, the funded projects will present their current status on open design tools and methods for analogue design. Participants will receive an overview of the contribution of the respective projects to the development of technology open, accessible, and sustainable design chains in the sense of the DE:Sign guideline.

If you have any questions, please contact the organizers by e-mail at: analog2026@ims.uni-hannover.de

Aalto Microelectronics Fair

Aalto Microelectronics Fair

March 20, 2026, 9.00-15.30

Aalto Yliopisto, Kandidaattikeskus, H304, Otakaari 1, 02150 Espoo

Time	Session
8:30–9:00	Morning coffee
9:00–9:15	Opening Aleksi Korsman
	Keynotes
9:15–10:00	Keynote 1: “OpenPDK - Global Scholar Platform”, Wladek Grabinski, Open PDK Initiative
10:05–10:50	Keynote 2: “Open Source Design Tools in SME IC Design Companies”, Ari Paasio, Kovilta
	Research overviews
11:00–11:15	Research overview: Kari Stadius
11:15–11:30	Research overview: Prof. Marko Kosunen
11:30–11:45	Research overview: Prof. Kwantae Kim
11:45–12:45	Lunch (and posters)
12:45–13:15	Student talk: “Five years of RISC‑V processor design at Aalto”, Aleksi Korsman
13:15–13:45	Student talk: “Beyond Neural Networks: Overcoming the Symbolic Bottleneck via Approximate Logarithm Acceleration”, Lingyun Yao
	Posters
13:45–14:00	Poster intro
14:00–15:00	Posters with coffee and snacks
15:00–15:30	Feedback and closing

Should you have any questions, please email Marko Kosunen

[C4P] MIXDES 2026

CALL FOR PAPERS

33rd International Conference

MIXED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS

MIXDES 2026

25 - 27 June 2026, Poznań, Poland

MIXDES Areas of Interest include:
1. Design of Integrated Circuits and Microsystems

Design methodologies. Digital and analog synthesis. Hardwaresoftware codesign. Reconfigurable hardware. Hardware description languages. Intellectual property-based design. Design reuse.

2. Thermal Issues in Microelectronics

Thermal and electro-thermal modelling, simulation methods and tools. Thermal mapping. Thermal protection circuits.

3. Analysis and Modelling of ICs and Microsystems

Simulation methods and algorithms. Behavioural modelling with VHDL-AMS and other advanced modelling languages. Microsystems modelling. Model reduction. Parameter identification.

4. Microelectronics Technology and Packaging

New microelectronic technologies. Packaging. Sensors and actuators.

5. Testing and Reliability

Design for testability and manufacturability. Measurement instruments and techniques.

6. Power Electronics

Design, manufacturing and simulation of power semiconductor devices. Hybrid and monolithic Smart Power circuits. Power integration.

7. Signal Processing

Digital and analogue filters, telecommunication circuits. Neural networks. Fuzzy logic. Low voltage and low power solutions.

8. Embedded Systems

Design, verification and applications.

9. Medical Applications

Medical and biotechnology applications. Biometrics. Thermography in medicine.10. Artificial Intelligence in Electronic SystemsAI-driven design. AI-driven signal and data processing. Edge AI.

Tutorials and Special Sessions Call for Proposals

Several tutorials/special sessions will be held prior to the conference. Authors willing to propose a tutorial at MIXDES 2026 are invited to send a proposal to the Organizing Committee. The proposal should consist of a three-page summary including tutorial title, name and affiliation of the lecturer(s), tutorial objectives and audience, topical outline and provisional schedule of the tutorial.

Enquiries:
Mariusz Orlikowski (Conference Secretary) e-mail: mixdes2026@dmcs.p.lodz.pl

Lodz University of Technology
Department of Microelectronics and Computer Science (K-22)
ul. Wólczańska 221 (building B18)

93-005 Łódź, Poland

tel.: +48 604397239
fax: +48 426360327

ISHI-kai OpenMPW

ISHI-kai (Inter-linked Society on Homemade IC Kai)

https://ishikai.connpass.com/event/382637/

The name was conceived from a society community (association) that deals with open (democratized) silicon semiconductor (ASIC/LSI/IC) and connects various R&D fields.

OpenMPW (Open Multi Project Wafer), which appeared as a pioneer of this, is a shuttle program born with Google's investment in Efabless, and is open and free of charge for semiconductors (ASIC/LSI/ICs), including the tools necessary for making semiconductors (ASIC/LSI/IC) to ISHI manufacturing in the fab. IC). This is exactly the "openness of semiconductors (ASIC/LSI/IC) and EDA/PDK" of the open source movement (democratization of software) that started with GNU! [read more...]

Time	Title	Speakers	Contents
20:00 - 20:30	End-to-end open-source Digital IC Design Participation Report	@jun1okamura/OpenSUSI	-
20:30 - 21:00	Various event reports such as academic conferences	@nishizawa#2174	-
21:00 - 21:30	I thought about the application of self-made LSIs that are no longer a niche	Yuuki Umeta/Newcomer	Although the base of self-made LSIs is expanding, there are still aspects that are established by public subsidies and donations from major companies. Therefore, it cannot be said that there is an established business model (with long-term financial sustainability). I thought it would be a hint for many people, so I thought about how to apply it like brainstorming.
21:30 - 22:00	The Game Participation Experience Report	@reodon	-
22:00 - 22:30	About the AX1001 SoC for SWEST27 Robots & IoT Edge	Susumu Yamazaki/SWEST27 Executive Committee & Associate Professor, Kitakyushu City University	This is a lecture given by Mr. Takeoka of Axe Co., Ltd. in SWEST27. The AX1001, a proprietary SoC developed for robots and IoT edges, is equipped with the ROS2rapper IP, which is a completely hardware-based ROS2 communication unit. At the same time, it is also equipped with a "Shochiku V" CPU that is an independent expansion of RISC-V. Shochiku V has multi-threaded control and semaphore by hardware, and realizes RTOS-equivalent functions only with hardware. Shochiku V also has an 8-bit floating-point vector arithmetic mechanism for ML and a Lisp/Prolog acceleration instruction.
22:30 - 23:00	Launch report of the ISHI Kai's GPS system on the Kagoshima rocket	@noritsuna	We will have the GPS system for rockets being created by the ISHI Association installed on the Kagoshima rocket and participate in the launch experiment. Therefore, we will report on the GPS system and the work of the rocket until the launch and the launch itself.
23:00 -	Chat Corner	Everyone	-

[rsvNumerics] hands-on transistor sizing for analog ICs

rsvNumerics – info@rsvn.ch

Copyright © 2025 rsvNumerics – All Rights Reserved

rsvNumerics provides concepts, guidance and software tools for sizing transistors in integrated circuits with an easy-to-learn methodology. Whether you are a novice or an expert, you can benefit from our methodology and dimension your devices in no time, serving as a near-perfect starting point for your verification. Moreover, our methodology is not limited to a few predefined circuit topologies; it works for literally any circuit in any application.

Constant-𝑔𝑚 Biasing Circuit Example 

rsvNumerics in Circuit Design General, SizingTool

The schematic of the constant-𝑔𝑚 bias circuit is shown above. It consists of two cross-coupled current mirrors, where one of the source contacts, e.g. of an NMOS transistor, is degenerated by a source resistor. This results in a unique operating point of the circuit other than zero current, which defines the pass current in the two branches.

The corresponding settings of SizingTool 3 for transistor 𝑁𝑀0 and for transistor 𝑁𝑀1 are given in Fig above. Once the drain currents for a constant-𝑔𝑚 biasing block are known, we can use the information when designing any other transistor with derived source current. However, there its drain current has to be readjusted each time the process corner is changed to reflect for constant-𝑔𝑚 biasing, which is tedious, and is addressed by the current weighing option.

Comments? Leave a Reply

[paper] Avalanche Multiplication in SiGe HBTs

Zhang, Huaiyuan, Guofu Niu, Andries J. Scholten, and Marnix B. Willemsen

"Avalanche Multiplication Factor Modeling and Extraction at High Currents in SiGe HBTs"

IEEE Transactions on Electron Devices (2025)

DOI: 10.1109/TED.2025.3558114

1. Auburn University, Auburn, AL, USA

2. NXP, Eindhoven, The Netherlands

Abstract: A new compact model and an extraction method for avalanche multiplication factor (M-1) at high currents are proposed. At a fixed collector–base (CB) voltage (VCB), M-1 first decreases with increasing emitter current (IE) and then increases at higher currents when the Kirk effect occurs. Different forced-IE M-1 extraction techniques are evaluated, including a new compact modeling-based M-1 extraction technique that accurately captures the Early effect, the Kirk effect, and self-heating. The model is implemented in a development version of MEXTRAM and demonstrated experimentally to model both the current and bias dependence of M-1 and base current (IB). 

FIG: Simplified dc equivalent circuit of a transistor under forced IE,VCB 

and  fT(IE) meas/sim up to 150 mA at VCB = 1, 2, and 3 V (b)

Acknowledgment: The authors wish to acknowledge the support of the Compact Model Coalition (CMC).

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