[paper] CMOS Technology for Analog Applications in High Energy Physics

Gianluca Traversi, Luigi Gaioni, Lodovico Ratti, Valerio Re and Elisa Riceputi

Characterization of a 28 nm CMOS Technology

for Analog Applications in High Energy Physics 

in IEEE Transactions on Nuclear Science

DOI: 10.1109/TNS.2024.3382348

1 INFN Pavia and Dipartimento di Ingegneria e Scienze Applicate, Uni. Bergamo, Italy
2 INFN Pavia and Dipartimento di Ingegneria Industriale e dell’Informazione, Uni. Pavia, Italy

Abstract: In the last few years, the 28 nm CMOS technology has raised interest in the High Energy Physics community for the design and implementation of readout integrated circuits for high granularity position sensitive detectors. This work is focused on the characterization of the 28 nm CMOS node with a particular focus on the analog performance. Small signal characteristics and the behavior of the white and 1/f noise components are studied as a function of the device polarity, dimensions, and bias conditions to provide guidelines for minimum noise design of front-end electronics. Comparison with data extracted from previous CMOS generations are also presented to assess the performance of the technology node under evaluation. 

Fig: Transconductance efficiency gm/ID as a function of the normalized

drain current IDL/W for NMOS (a) and PMOS (b) devices (|VDS| = 0.9 V)

Acknowledgment: The activity leading to the results presented in this paper was carried out in the framework of the Falaphel project, funded by the Italian Institute for Nuclear Physics (INFN). The authors wish to thank Prof. Massimo Manghisoni (University of Bergamo) for the valuable advice which contributed to improve this work and Dr. Stefano Bonaldo (University of Padova) for fruitful discussions on the measurement results. The authors wish to thank also Barbara Pini (INFN Torino) for the wire bonding of the chips, Emilio Meroni and Nicola Cattaneo (University of Bergamo) for the characterization activity.

[paper] Noise Characterization of MOSFETs for Cryogenic Electronics

Variable-Temperature Broadband Noise Characterization of MOSFETs

for Cryogenic Electronics: From Room Temperature down to 3K

Kenji Ohmori¹ and Shuhei Amakawa²

TechRxiv. DETM 2022 Preprint

DOI: 10.36227/techrxiv.21762917.v1

1 Device Lab Inc., Tsukuba, Ibaraki, Japan,

2 Hiroshima University, Higashihiroshima, Hiroshima, Japan

Abstract: A broadband noise measurement system is newly developed and demonstrated at temperatures between 3K and 300K. Using the system, wideband noise spectroscopy (WBNS) from 20kHz to 500MHz is carried out for the first time, revealing that shot noise is the dominant white noise down to 3K. The paper also suggests, by means of WBNS, the possibility of extracting the baseline noise characteristics, which do not include the noise component that varies a great deal from device to device.

FIG: a.) IdVg Curves at T = 2.9K ... 300K and b.) 1/f Noise at T=5K

Acknowledgement: 

This work was partially supported by NEDO-SBIR.

[paper] Charge Trapping/Detrapping in Scaled MOSFETs

Ruben Asanovski, Pierpaolo Palestri*, and Luca Selmi

Importance of Charge Trapping/Detrapping Involving the Gate Electrode on the Noise Currents of Scaled MOSFETs

IEEE TED, Vol. 69, No. 3, March 2022 1313

DOI: 10.1109/TED.2022.3147158

  

 Università degli Studi di Modena e Reggio Emilia, Modena, Italy

*Università degli Studi di Udine, Udine, Italy

Abstract: Carrier trapping/detrapping from/to the gate into dielectric traps is often neglected when modeling noise in MOSFETs and, to the best of our knowledge, no systematic study of its impacts on scaled devices is available. In this article, we show that this trapping mechanism cannot be neglected in nowadays aggressively scaled gate dielectric thicknesses without causing errors up to several orders of magnitude in the estimation of the drain current noise. The noise generation mechanism is modeled analytically and then analyzed through the use of 2-D and 3-D TCAD simulations of scaled MOSFETs with different architectures and channel/gate-stack materials. The results provide new insights for technology and device designers, highlight the relevance of the choice of the gate metal work function (WF) and the role of valence band electron trapping at high gate voltages.

Fig: (a) FinFET with the single trap location highlighted. (b) Drain current noise comparison between TCAD simulations at VGS = 0.7 V, VDS = 25 mV and single trap located as in (a).

[book] The Random and Fluctuating World

The Random and Fluctuating World
Celebrating Two Decades of Fluctuation and Noise Letters

February 2022 Pages: 640

Edited By: 

P V E McClintock (Lancaster University, UK) and 

L B Kish (Texas A&M University, USA)

DOI: 10.1142/12720 | 

Description: It is now almost 20 years since the journal Fluctuation and Noise Letters (FNL) was first published hence this book is to commemorate this important milestone. This book consists of 55 reprinted articles from the first 20 years of FNL, together with a short Introduction explaining their context and significance. In selecting the papers, the Editors had taken into account not only citation counts, but guided also by the perceived interest and scientific importance of the work. All selected articles are arranged across eight themes.

Contents:

• Acknowledgments
• Preface
• Introduction
• Fundamentals of Noise
• Noise in Quantum Systems
• Noise in Complex Systems
• Noise in Biological Systems
• Noise in Materials, Circuitry, Devices and Sensing
• Noise, Computation and Energy Dissipation
• Noise in Finance
• Noise and Security in Communications
• Author Index

Readership: Physicists, chemists, materials scientists, engineers, biologists, medical scientists, IT specialists, social scientists, economists, advanced graduate students.

[papers] Compact/SPICE Modeling

[1] Wang, Jie; Chen, Zhanfei; You, Shuzhen; Bakeroot, Benoit; Liu, Jun; Decoutere, Stefaan; "Surface-Potential-Based Compact Modeling of p-GaN Gate HEMTs" Micromachines (2021) 12, no. 2: 199; https://doi.org/10.3390/mi12020199

Abstract: We propose a surface potential (SP)-based compact model of p-GaN gate high electron mobility transistors (HEMTs) which solves the Poisson equation. The model includes all possible charges in the GaN channel layer, including the unintended Mg doping density caused by out-diffusion. The SP equation and its analytical approximate solution provide a high degree of accuracy for the SP calculation, from which the closed-form I–V equations are derived. The proposed model uses physical parameters only and is implemented in Verilog-A code.

Fig: The equivalent circuit of the capacitance of field plates (FPs) of a p-GaN gate HEMT.

[2] Chen, H. and He, L.,  The spatial and energy distribution of oxide trap responsible for 1/f noise in 4H-SiC MOSFETs. Journal of Physics Communications, JPCO-101816.R1 (2021)

Abstract: Low-frequency noise is one of the important characteristics of 4H-SiC metal-oxide-semiconductor field-effect transistors (MOSFETs) that is susceptible to oxide traps. Drain-source voltage noise models of 4H-SiC MOSFETs under low–drain-voltage and inverse condition were proposed by considering the spatial and energy non-uniform distribution of the oxide trap, based on the McWhoter model for uniform trap distribution. This study performed noise experiments on commercial 4H-SiC MOSFETs, and revealed that the non-uniform spatial and non-uniform energy distribution caused new 1/f noise phenomenon, different from that under uniform spatial and energy distribution. By combining experimental data and theoretical models, the spatial and energy distribution of oxide traps of these samples were determined.

Fig: Adaptive circuit for 4H-SiC MOSFET noise measurement

in the frequency 1 Hz-10kHz ranged

[paper] LF Noise Characterization of Ge n-Channel FinFETs

Alberto V. de Oliveira (Member, IEEE), Duan Xie (Member, IEEE), Hiroaki Arimura, Guillaume Boccardi, Nadine Collaert, Cor Claeys (Fellow, IEEE), Naoto Horiguchi (Member, IEEE)

and Eddy Simoen (Senior Member, IEEE_

Low-Frequency Noise Characterization of Germanium n-Channel FinFETs

IEEE Transactions on Electron Devices, vol. 67, no. 7, pp. 2872-2877, July 2020

DOI: 10.1109/TED.2020.2990714

Abstract: This article presents an experimental, room temperature, low-frequency noise characterization of germanium n-channel fin-field-effect transistors (finFETs) integrated on silicon. After determining the dominant mechanism in the noise spectrum, the main parameters associated with the noise mechanism are extracted and evaluated as a function of fin width from a planar-like (100 nm) up to narrow fin (20 nm) for 1-µm length devices. The main findings are that the 1/f noise plays an important role in the Ge n-finFETs, whereby the trap density profiles in the gate-stack are quite uniform and have a lower level than in n-/p-channel Ge planar MOSFETs. In addition, a generation-recombination (GR) component was found in 160-nm-length devices, which is caused by GR centers located in the depletion region.

Fig: (a) Schematic of the Ge  n-finFET structure 

and (b) gate-stack composition

Fig: Drain current noise power spectral density as a function of frequency 

for a 160nm long Ge n-finFET

Acknowledgment: The authors would like to thank the Coordenação de Aperfeiçoamento de Pessoal de Nível Superior (CAPES) and the Logic IIAP program for the support. This work has been performed in the frame of the imec Core Partner program on Ge devices.

ICNF 2017: 2nd Call for Papers

24th International Conference on Noise and Fluctuations (ICNF 2017) 

20-23 of June 2017 in Vilnius, Lithuania

We would like to invite you to submit your abstracts. For submission of the abstracts, please, REGISTER and go to the Abstract submission site. Instruction for authors and templates for abstract preparation can be found and downloaded  at the Conference website: http://www.icnf2017.ff.vu.lt/paper-submission/instructions-for-authors
Deadline of the abstract submission is 22 January, 2017

Please also keep in mind ICNF2017 important dates:

• Abstract submission deadline: 22 January, 2017
• Notification of acceptance deadline: 27 February, 2017
• Full paper submission deadline:27 March, 2017
• Early bird registration: 19 April, 2017
• Conference: 20-23 June, 2017

Please share this information to your colleagues and those who might be interested in ICNF 2017.

For more information visit the Conference website: http://www.icnf2017.ff.vu.lt/
or contact us: icnf2017@ff.vu.lt

Looking forward to meeting you in Vilnius.

With best regards,
Sandra Pralgauskaitė and Paulius Sakalas - Organizing Committee Chairs

[ESSDERC Paper] Compact model for variability of low frequency noise due to number fluctuation effect

Compact model for variability of low frequency noise due to number fluctuation effect

N. Mavredakis and M. Bucher

2016 46th European Solid-State Device Research Conference (ESSDERC)

Lausanne, Switzerland, 2016, pp. 464-467

doi:10.1109/ESSDERC.2016.7599686

Abstract: Variability of low frequency noise (LFN) in MOSFETs is both geometry- and bias-dependent. RTS noise prevails in smaller devices where noise deviation is mostly area-dominated. As device dimensions increase, operating conditions determine noise variability maximizing it in weak inversion and increasing it with drain voltage. This dependence is shown to be directly related with fundamental carrier number fluctuation effect. A new bias- and area-dependent, physics-based, compact model for 1/f noise variability is proposed. The model exploits the log-normal behavior of LFN. The model is shown to give consistent results for average noise, variance, and standard deviation, covering bias-dependence and scaling over a large range of geometry.

Keywords: compact models, Low-frequency noise, MOSFET, Reactive power, Semiconductor device modeling, Shape, Standards, MOSFET, low frequency noise, noise variability

URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7599686&isnumber=7598672

[Summer Tutorial] Verified Measurements for Successful Device Models

 Verified Measurements for Successful Device Models 

 at IHP in Frankfurt (Oder), June 15-17, 2016 

Good electronic device modeling results depend directly on reliable, qualified and verified measurements. It is a known fact that problems with device models are – to a big part – rather due to measurement problems. Within the measurement chain of DC, Impedance (CV), S-Parameter, Nonlinear RF, and Noise, there are several challenges to overcome like device self-heating, contact resistance, max. applicable RF power, calibration, de-embedding etc.

IHP Summer Tutorial will take place at IHP in Frankfurt (Oder), June 15-17, 2016. It will cover in detail all these measurement domains, will explain the setups, the data verification methods, the traps to be avoided, and give best-practice recommendations and examples. It will be enhanced by live measurements in IHP’s measurement labs.

As a wrap-up, an introduction into device modeling, applying the qualified and verified measurements, will be given at the end.

Who should attend: Semiconductor manufacturing and measurement engineers, device modeling engineers, scientists and students working/interested in measurement techniques.

[Course Schedule]