[1] Nicolo Zagni; Simulation and Modeling Methods for Predicting Performance and Reliability Limits of 21st-Century Electronics; PhD Thesis, Universita Degli Estudi Di Modena e Reggio Emilia; Anno Accademico 2019–2020 (CICLO XXXIII)
Abstract: In recent years, a plethora of novel semiconductor devices have started emerging as worthy heirs of Silicon-based transistors – giving rise to the ’post-Moore’ era. Traditional electronics is mostly based on Si devices, – from logic to memory, to high frequency/power and sensing applications – but this paradigm is changing thanks to the developments in different fields ranging from physics and semiconductor materials, to processing techniques and computing architectures. In this hectic new scenario, before even considering a new technology as a replacement of the existing ones, the limiting factors to its performance and reliability need to be well-understood and engineered for. In this sense, simulations and physics-based modeling represent critical tools to make sure that newly conceived technologies stand up to the requirements of 21st century electronics. In this thesis, state-of-the-art simulation and compact modeling tools are exploited to analyze the performance and reliability limits of several emerging technologies. Specifically, this dissertation is focused on four application scenarios and the relative candidate technologies that aim to providing enhanced performance/reliability compared to Si-based counterparts. These are: i) III-V MOSFETs for logic/digital circuits, ii) resistive-RAMs and ferroelectric-FETs for non-volatile memory and in-memory computing, iii) GaN-based high-speed transistors for power applications, and iv) negative capacitance transistors for biosensing.
Fig: Energy bandgap (Eg) vs lattice constant (a) of different semiconductor materials, showing that In0.57Ga0.43As has the same lattice constant as InP. Adapted from: https://www.iue.tuwien.ac.at/phd/brech/diss.htm (visited on 12/20/2020).
[2] G. Maroli, A. Fontana, S. M. Pazos, F. Palumbo and P. Julián, "A Geometric Modeling Approach for Flexible, Printed Square Planar Inductors under Stretch," 2021 Argentine Conference on Electronics (CAE), Bahia Blanca, Argentina, 2021, pp. 61-66, DOI: 10.1109/CAE51562.2021.9397568.
Abstract: In this work a compact model for square planar inductors printed on flexible substrate is proposed. The approach considers the deformation of the metal traces of square spiral inductors when the substrate is subjected to physical stretch. The model considers a typical pi-network for the device, where each component is calculated for different stretching values adapting widely accepted models on the literature for the total inductance, the AC resistance and the ground coupling and inter-wounding capacitances. Model results are contrasted to 3D full electromagnetic wave simulations under parametric sweeps of the dimensions calculated under stretch. Results show good agreement within a 20 % stretch up to the first resonance frequency of the structure. The model can prove useful for the optimization of component design for printed applications on flexible substrates.
[3] H. Kikuchihara et al., "Modeling of SJ-MOSFET for High-Voltage Applications with Inclusion of Carrier Dynamics during Switching," 2021 International Symposium on Devices, Circuits and Systems (ISDCS), Higashihiroshima, Japan, 2021, pp. 1-4, DOI: 10.1109/ISDCS52006.2021.9397904.
Abstract: Demands for higher-voltage MOSFET application are increasing, for which a Super-Junction MOSFET, sustaining the voltages in the range of 500V, has been developed based on the trench-type structure. Due to the huge bias applied, a new leakage-current type is induced during switching, which causes a switching-power-loss increase. Creating a compact model for circuit design, which includes this additional leakage current, is the purpose of the present development. The model describes the depletion-width variation, caused during the switching-on of the device, with the use of the internal node potential, determined accurately by iteration. It is verified, that the new compact model can accurately predict the device performances for different device structures. This capability can be used for device optimization to realize low-power circuitry.
