[book] Negative Capacitance Field Effect Transistors

Negative Capacitance Field Effect Transistors

Physics, Design, Modeling and Applications

Edited By Young Suh Song, Shubham Tayal, Shiromani Balmukund Rahi, Abhishek Kumar Upadhyay

Pages 63 Color & 7 B/W Illustrations

ISBN 9781032445311 176 Sept. 29, 2023 by CRC Press

Description

This book aims to provide information in the ever-growing field of low-power electronic devices and their applications in portable device, wireless communication, sensor, and circuit domains. Negative Capacitance Field Effect Transistor: Physics, Design, Modeling and Applications, discusses low-power semiconductor technology and addresses state-of-art techniques such as negative-capacitance field-effect transistors and tunnel field-effect transistors. The book is broken up into four parts. Part one discusses foundations of low-power electronics including the challenges and demands and concepts like subthreshold swing. Part two discusses the basic operations of negative-capacitance field-effect transistor (NC-FET) and Tunnel Field-effect Transistor (TFET). Part three covers industrial applications including cryogenics and biosensors with NC-FET. This book is designed to be one-stop guidebook for students and academic researchers, to understand recent trends in the IT industry and semiconductor industry. It will also be of interest to researchers in the field of nanodevices like NC-FET, FinFET, Tunnel FET, and device-circuit codesign.

Table of Contents

Chapter 1 Recent Challenges in IT and Semiconductor Industry: From Von Neumann Architecture to the Future

Young Suh Song, Shiromani Balmukund Rahi, Navjeet Bagga, Sunil Rathore, Rajeewa Kumar Jaisawal, P. Vimala, Neha Paras, K. Srinivasa Rao

Chapter 2 Technical Demands of Low-Power Electronics

Soha Maqbool Bhat, Pooran Singh, Ramakant Yadav, Shiromani Balmukund Rahi, Billel Smaani, Abhishek Kumar Upadhyay, Young Suh Song

Chapter 3 Negative capacitance Field Effect Transistors: Concept and Technology

Ball Mukund Mani Tripathi

Chapter 4 Basic Operation Principle of Negative Capacitance Field Effect Transistor

Malvika, Bijit Choudhuri, Kavicharan Mummaneni

Chapter 5 Basic Operational Principle of Anti-ferroelectric Materials and Ferroelectric Materials

Umesh Chandra Bind, Shiromani Balmukund Rahi

Chapter 6 Basic Operation Principle of Optimized NCFET: Amplification Perspective

S. Yadav, P.N Kondekar, B. Awadhiya

Chapter 7 Spin Based Magnetic Devices With Spintronics

Asif Rasool, Shahnaz kossar, R.Amiruddin

Chapter 8 Mathematical Approach for Future Semiconductor Roadmap

Shiromani Balmukund Rahi,Abhishek Kumar Upadhyay, Young Suh Song, Nidhi Sahni, Ramakant Yadav, Umesh Chandra Bind,Guenifi Naima,Billel Smaani,Chandan Kumar Pandey,Samir Labiod, T.S. Arun Samul,Hanumanl Lal, H. Bijo Josheph

Chapter 9 Mathematical Approach for Foundation of Negative Capacitance Technology

Shiromani Balmukund Rahi,Abhishek Kumar Upadhyay, Young Suh Song, Nidhi Sahni, Ramakant Yadav, Umesh Chandra Bind,Guenifi Naima,Billel Smaani,Chandan Kumar Pandey,Samir Labiod, T.S. Arun Samul,Hanumanl Lal, H. Bijo Josheph

[paper] Microchips for Memristive Applications

Kaichen Zhu, Sebastian Pazos, Fernando Aguirre, Yaqing Shen, Yue Yuan, Wenwen Zheng, Osamah Alharbi, Marco A. Villena, Bin Fang, Xinyi Li, Alessandro Milozzi, Matteo Farronato, Miguel Muñoz-Rojo, Tao Wang, Ren Li, Hossein Fariborzi, Juan B. Roldan, Guenther Benstetter, Xixiang Zhang, Husam N. Alshareef, Tibor Grasser, Huaqiang Wu, Daniele Ielmini & Mario Lanza 

Hybrid 2D–CMOS microchips for memristive applications

Nature 618, 57–62 (2023)

DOI: 10.1038/s41586-023-05973-1

Abstract: Exploiting the excellent electronic properties of two-dimensional (2D) materials to fabricate advanced electronic circuits is a major goal for the semiconductor industry1,2. However, most studies in this field have been limited to the fabrication and characterization of isolated large (more than 1 µm2) devices on unfunctional SiO2–Si substrates. Some studies have integrated monolayer graphene on silicon microchips as a large-area (more than 500 µm2) interconnection3 and as a channel of large transistors (roughly 16.5 µm2) (refs. 4,5), but in all cases the integration density was low, no computation was demonstrated and manipulating monolayer 2D materials was challenging because native pinholes and cracks during transfer increase variability and reduce yield. Here, we present the fabrication of high-integration-density 2D–CMOS hybrid microchips for memristive applications—CMOS stands for complementary metal–oxide–semiconductor. We transfer a sheet of multilayer hexagonal boron nitride onto the back-end-of-line interconnections of silicon microchips containing CMOS transistors of the 180 nm node, and finalize the circuits by patterning the top electrodes and interconnections. The CMOS transistors provide outstanding control over the currents across the hexagonal boron nitride memristors, which allows us to achieve endurances of roughly 5 million cycles in memristors as small as 0.053 µm2. We demonstrate in-memory computation by constructing logic gates, and measure spike-timing dependent plasticity signals that are suitable for the implementation of spiking neural networks. The high performance and the relatively-high technology readiness level achieved represent a notable advance towards the integration of 2D materials in microelectronic products and memristive applications.

FIG: Structure of the considered SNN. Each MNIST image is reshaped as a 784x1 column vector, and the intensity of the pixels is encoded in terms of the firing frequency of the input neurons. The only trainable synapses are those connecting the input layer with the excitatory layer, and they are modelled with the STDP characteristic of the CMOS-h-BN based 1T1M cells. The learning is unsupervised, and the neurons are labelled only after the training. These label-neuron assignments are then feed to the decision block altogether with the firing patterns of the neurons, to infer the class of the image presented in the input. 

Acknowledgements: This work has been supported by the Ministry of Science and Technology of China (grant nos. 2019YFE0124200 and 2018YFE0100800), the National Natural Science Foundation of China (grant no. 61874075) and the Baseline funding scheme of the King Abdullah University of Science and Technology.

UPCOMING – Winter School in III-Sb applications

UPCOMING

Winter School in III-Sb applications: non-volatile memories

A Modelling Perspective

QUANTIMONY’s Winter School in III-Sb Applications: non-volatile Memories: a Modelling Perspective will take place from February 27th to March 3rd 2023 at the premises of the Technical University of Berlin.

The 5-day event will focus on the design and scalable production of a new III-Sb patented memory device (ULTRARAM TM). There will be a combination of specialised lectures by international experts, and hands-on tutorials/lab sessions as well as live demonstrations of the latest TCAD/EDA tools organised by the Technical University of Berlin.

The event will provide with an excellent opportunity for networking with leaders in the field.

List of Confirmed Speakers Invited Speakers and Hands - on Session:

• Prof. Dr. Manus Hayne, Lancaster University Birth of the ULTRARAM TM Concept
• Prof. Dr. Dieter Bimberg, Technische Universität Berlin Quantum Dot-Based Flash Memories: The Holy Grail at Sunrise?
• Dr. Petr Klenovský, Masaryk University, Brno Modeling Electronic states of IlI-Sb guantum systems on GaP substrate
• Dr. Wladek Grabinski, MOS-AK (EU) FOSS TCAD/EDA Tools for Compact Modeling
• Prof. Vihar Georgiev, James Watt School of Engineering, Glasgow Nano-electronic Simulation Software (NESS): a flexible nano-device simulation platform
• PD Dr. Uwe Bandelow, WIAS Berlin TBA
• Prof. Claudia Dr.axl, Humboldt Universität Berlin Unsupervised learning for insight into high-throughput calculations
• Rabea Pons, Comsol, Göttingen Introduction into COMSOL and hands-on session
• Prof. Dr. Mathieu Luisier, ETH Zürich TBA
• Dr. Marc Bescond, Faculté des Sciences de Saint Jérôme, NQS group, Marseille TBA
• Dr. Chetan Gupta, Micron Technology (R&D) Industry perspective on memory technologies
• Prof. Dr. Jannik Wolters, Deutschen Zentrum für Luft- und Raumfahrt / TU Berlin Quantum Memories and Introduction into Quantum Technologie

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