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Nanoscale Electronic Device Applications of Carbon Nanotubes,

Graphene, Silicene and Molybdenum Disulfide

[paper] p-Type Doped Silicene-based

Mu Wen Chuan, Munawar Agus Riyadi, Afiq Hamzah, Nurul Ezaila Alias, Suhana Mohamed Sultan, Cheng Siong Lim, Michael Loong Peng Tan

Device performances analysis of p-type doped silicene-based field effect transistor using SPICE-compatible model

PLoS ONE 17(3): e0264483.: March 3, 2022

DOI: 10.1371/journal.pone.0264483

   
Universiti Teknologi Malaysia, Skudai, Johor, Malaysia
Diponegoro University, Semarang, Indonesia

Abstract: Moore’s Law is approaching its end as transistors are scaled down to tens or few atoms per device, researchers are actively seeking for alternative approaches to leverage more-than-Moore nanoelectronics. Substituting the channel material of a field-effect transistors (FET) with silicene is foreseen as a viable approach for future transistor applications. In this study, we proposed a SPICE-compatible model for p-type (Aluminium) uniformly doped silicene FET for digital switching applications. The performance of the proposed device is benchmarked with various low-dimensional FETs in terms of their on-to-off current ratio, subthreshold swing and drain-induced barrier lowering. The results show that the proposed p-type silicene FET is comparable to most of the selected low-dimensional FET models. With its decent performance, the proposed SPICE-compatible model should be extended to the circuit-level simulation and beyond in future work.

Fig: Schematic diagrams of AlSi3 FET: (a) the structure and 

(b) the ToB nanotransistor circuit model. 

Acknowledgements: 1.) Michael Tan Loong Peng - Ministry of Higher Education (MOHE) of Malaysia through the Fundamental Research Grant Scheme(FRGS/1/2021/ STG07/ UTM/02/3); The funders had no role in study design, data collection and analysis, decision to publish, or preparation of the manuscript. 2.) Munawar Agus Riyadi - World Class Research Universitas Diponegoro (WCRU) 2021 Grant no. 118-16/UN7.6.1/PP/2021; The funders had no role in study design, data collection and analysis, decision to publish, or preparation of the manuscript.

[review] CNTFET Technology for RF Applications

CNTFET Technology for RF Applications: Review and Future Perspective 

Martin Hartmann^1,2, Sascha Hermann^1,2,3, Phil F. Marsh⁴, Christopher Rutherglen⁴, 

Dawei Wang⁵, Li Ding⁶, Lian-Mao Peng⁶, Martin Claus⁷ 

and Michael Schröter⁷ (Senior Member, IEEE)

(Invited Paper)

in IEEE Journal of Microwaves, vol. 1, no. 1, pp. 275-287, winter 2021, 

DOI: 10.1109/JMW.2020.3033781

1Center for Microtechnology, Chemnitz University of Technology, 09111 Chemnitz, Germany
2Center for Advancing Electronics Dresden, 09111 Chemnitz, Chemnitz
3Fraunhofer Institute for Electronic Nanosystems, 09126 Chemnitz, Germany
4Carbonics Inc., Culver City, CA 90230 USA
5Carbon Technology Inc., Irvine, CA 92619 USA
6Key Laboratory for the Physics and Chemistry of Nanodevices and Center for Carbon-based Electronics, Department of Electronics, Peking University, Beijing 100871, China
7Chair for Electron Devices and Integrated Circuits, Technical University Dresden, 01069 Dresden, Germany

Abstract: RF CNTFETs are one of the most promising devices for surpassing incumbent RF-CMOS technology in the near future. Experimental proof of concept that outperformed Si CMOS at the 130 nm technology has already been achieved with a vast potential for improvements. This review compiles and compares the different CNT integration technologies, the achieved RF results as well as demonstrated RF circuits. Moreover, it suggests approaches to enhance the RF performance of CNTFETs further to allow more profound CNTFET based systems e.g., on flexible substrates, highly dense 3D stacks, heterogeneously combined with incumbent technologies or an all-CNT system on a chip.

Fig: (a) sketch of a T-shape top gate on 4′′ wafer and (b) corresponding SEM image, (c) SEM image [I] in false colors depicting a multifinger buried gate CNTFET on an 8" wafer [II].

Acknowledgement: This work was supported in part by the German Research Foundation (DFG) through the Cluster of Excellence “Center for Advancing Electronics Dresden” (EXC1056/1); in part by the Federal Ministry of Education and Research under the project reference numbers 16FMD01K, 16FMD02 and 16FMD03, under the individual DFG Grant SCR695/6%25; in part by the National Key Research & Development Program under Grant 2016YFA0201901; in part by the National Science Foundation of China under Grants 61888102 and 61671020; in part by the Beijing Municipal Science and Technology Commission under Grant Z181100004418011; in part by the King Abdulaziz City for Science and Technology (KACST); in part by The Saudi Technology Development and Investment Company (TAQNIA); in part by the U.S. Army STTR Contract W911NF19P002; and in part by the SBIR programs from the U.S. National Science Foundation and the U.S. Air Force Research Laboratory.

REF:

[I] C. Rutherglen et al., "Wafer-scalable aligned carbon nanotube transistors operating at frequencies of over 100 GHz", Nature Electron., vol. 2, no. 11, pp. 530-539, 2019.

[II] M. Hartmann et al., "Gate spacer investigation for improving the speed of high-frequency carbon nanotube-based field-effect transistors", ACS Appl. Mater. Interfaces, vol. 12, no. 24, pp. 27461-27466, 2020.

[paper] CNTFET Technology for RF Applications

Martin Hartmann^1,2, Sascha Hermann^1,2,3, Phil F. Marsh⁴, Christopher Rutherglen⁴, 

Dawei Wang⁵, Li Ding⁶, Lian-Mao Peng⁶, Martin Claus⁷, 

and Michael Schröter⁷ (Senior Member, IEEE)

CNTFET Technology for RF Applications:

Review and Future Perspective

(Invited Paper)

IEEE Journal of Microwaves, vol. 1, no. 1, pp. 275-287, 2021

DOI: 10.1109/JMW.2020.3033781

¹Center for Microtechnology, Chemnitz University of Technology, Chemnitz, Germany
²Center for Advancing Electronics Dresden, Germany
³Fraunhofer Institute for Electronic Nanosystems, Chemnitz, Germany
⁴Carbonics Inc., Culver City, USA
⁵Carbon Technology Inc., Irvine, USA
⁶Key Laboratory for the Physics and Chemistry of Nanodevices 

and Center for Carbon-based Electronics,  Peking University, China
⁷Chair for Electron Devices and Integrated Circuits, Technical University Dresden, Germany

Abstract: RF CNTFETs are one of the most promising devices for surpassing incumbent RF-CMOS technology in the near future. Experimental proof of concept that outperformed Si CMOS at the 130 nm technology has already been achieved with a vast potential for improvements. This review compiles and compares the different CNT integration technologies, the achieved RF results as well as demonstrated RF circuits. Moreover, it suggests approaches to enhance the RF performance of CNTFETs further to allow more profound CNTFET based systems e.g., on flexible substrates, highly dense 3D stacks, heterogeneously combined with incumbent technologies or an all-CNT system on a chip.

Fig: (a) sketch of a T-shape top gate on 4" wafer and (b) corresponding SEM image,

(c) SEM image in false colors depicting a multifinger buried gate CNTFET on an 8" wafer.

Acknowledgement: This work was supported in part by the German Research Foundation (DFG) through the Cluster of Excellence “Center for Advancing Electronics Dresden” (EXC1056/1); in part by the Federal Ministry of Education and Research under the project reference numbers 16FMD01K, 16FMD02 and 16FMD03, under the individual DFG Grant SCR695/6%25; in part by the National Key Research & Development Program under Grant 2016YFA0201901; in part by the National Science Foundation of China under Grants 61888102 and 61671020; in part by the Beijing Municipal Science and Technology Commission under Grant Z181100004418011; in part by the King Abdulaziz City for Science and Technology (KACST); in part by the The Saudi Technology Development and Investment Company (TAQNIA); in part by the U.S. Army STTR Contract W911NF19P002; and in part by the SBIR programs from the U.S. National Science Foundation and the U.S. Air Force Research Laboratory.

[paper] Compact Modeling of Carbon Nanotube FETs

A Compact and Robust Technique for the Modeling and Parameter Extraction 

of Carbon Nanotube Field Effect Transistors

Laura Falaschetti¹, Davide Mencarelli¹, Nicola Pelagalli¹, Paolo Crippa¹, Giorgio Biagetti¹,

Claudio Turchetti¹,George Deligeorgis², and Luca Pierantoni¹

Electronics 2020, 9(12), 2199; 

DOI: 10.3390/electronics9122199

1 Department of Information Engineering, Marche Polytechnic University, 60131 Ancona, Italy
2 Microelectronics Research Group (MRG/IESL), FORTH, Greece

Abstract: Carbon nanotubes field-effect transistors (CNTFETs) have been recently studied with great interest due to the intriguing properties of the material that, in turn, lead to remarkable properties of the charge transport of the device channel. Downstream of the full-wave simulations, the construction of equivalent device models becomes the basic step for the advanced design of high-performance CNTFET-based nanoelectronics circuits and systems. In this contribution, we introduce a strategy for deriving a compact model for a CNTFET that is based on the full-wave simulation of the 3D geometry by using the finite element method, followed by the derivation of a compact circuit model and extraction of equivalent parameters. We show examples of CNTFET simulations and extract from them the fitting parameters of the model. The aim is to achieve a fully functional description in Verilog-A language and create a model library for the SPICE-like simulator environment, in order to be used by IC designers.

Figure 2. 3D structure of CNTFET. Reprinted, with permission, from [I and II]

Aknowlwgement: This research was supported by the European Project “NANO components for electronic SMART wireless circuits and systems (NANOSMART)”, H2020—ICT-07-2018-RIA, n. 825430.

References:

[I] Deng, J.; Wong, H.P. A Compact SPICE Model for Carbon-Nanotube Field-Effect Transistors Including non-idealities and Its Application—Part I: Model of the Intrinsic Channel Region. IEEE Trans. Electron Devices 2007, 54, 3186–3194

[II] Deng, J.; Wong, H.P. A Compact SPICE Model for Carbon-Nanotube Field-Effect Transistors Including non-idealities and Its Application—Part II: Full Device Model and Circuit Performance Benchmarking. IEEE Trans. Electron Devices 2007, 54, 3195–3205