[workshop] QC:DCEP 2023

Workshop on

Quantum Computing: Devices, Cryogenic Electronics and Packaging

A Seasonal School of the IEEE Circuits & Systems Society

Tues/Wed, 24-25 October, 2023 at SEMI World Hdqtrs, Milpitas, CA USA

Welcome to the first year of this new Workshop from the IEEE Circuits and Systems Society, organized and run by three Silicon Valley IEEE chapters: Circuits and Systems, Electron Devices and Electronics Packaging.

QC:DCEP 2023 is planned to be a hybrid event, with both in-person and WebEx participation. Registration is now open. On-site seating is limited. Review the Advance Program.

The intent of this workshop is to bring together engineers of electrical, mechanical, materials and computer science disciplines and physicists to describe the state-of-the-art in all the interconnected fields and the opportunities and challenges for future generations of quantum computers.

Confirmed plenary and invited talks:

Technical Challenges facing Quantum Computing with Superconducting Transmon Qubits Dr. Daniel Tennant, Rigetting Computing		Superconducting Multi-Chip Module (SMCM) Rabindra N. Das, MIT Lincoln Laboratory
Introduction to Quantinuum and TKET Dr. Kathrin Spendier, Quantinuum		Understanding and Addressing Challenges in Superconducting Qubit Scale Jennifer Smith, UC-Santa Barbara
Integrated Quantum-Classical Applications with CUDA Quantum Dr. Jin-Sung Kim, NVIDIA		A 22nm FD-SOI-CMOS Scalable Quantum Processor SoC with Fully Integrated Control Electronics at 3.5K Dr. Imran Bashir, Equal1
Network Architecture for a Scalable Spin Qubit Processor Prof. Jonathan Baugh, Univ. of Waterloo		Quantum Computing with Silicon Spins Dr. Dominik Zumbuhl, Univ of Basel
Quantum Error Correction in Bosonic Qubits Marina Kudra, PhD, Intermodulation Products		Thermal Management Challenges in Cryogenic System Integration: Spin Qubit Biasing with a CMOS DAC at mK Temperature Lea Schreckenberg, Forschungszentrum Jülich GmbH

plus additional technical talks 

Drawings will be held for two GeForce RTX-4090 graphics cards, donated by NVIDIA — one will be awarded to an on-site speaker, while the other will be awarded to an on-site attendee. These new gaming accelerators for Windows PCs are not yet on sale. Need not be present to win. We invite you to register for QC:DCEP 2023 using our EventBrite site. Register today!

[paper] Three-Gated Reconfigurable FETs

Giulio Galderisi, Christoph Beyer, Thomas Mikolajick, and Jens Trommer 

Insights into the Temperature Dependent Switching Behaviour of Three-Gated Reconfigurable Field Effect Transistors 

physica status solidi (a) DOI: 10.1002/pssa.202300019

NaMLab gGmbH Dresden (D) 

TU Dresden, Chair of Nanoelectronics, Dresden (D) 

Abstract: Three-Gated Reconfigurable Field Effect Transistors are innovative nanoelectronic devices that are rapidly and increasingly attracting substantial interest in several fields of application thanks to their inherent n-type/p-type reconfiguration capabilities. For this reason, it is of significant importance to acquire a deeper knowledge about the temperature ranges in which such devices can be operated and, at the same time, gather a better understanding of the physical mechanisms that are involved in their operation. To achieve this aim, in-depth observations about the functioning of such devices in an ultra-wide temperature range, spanning from 80 K to 475 K, were performed and are presented for their ambipolar and lowVT operation modes. In view of the data exhibited in this work, it is possible to assess the performances of Three-Gated Reconfigurable Field Effect Transistors within a considerable temperature span and finally provide significant insights on the temperature dependent physical mechanisms regulating their functionality.

FIG: a) Typical Three-Gated RFET transfer characteristic, showing both p-/n-type curves for lowVT and highVT operations together with the ambipolar mode. b) Cross-sectional depiction of a Three-Gated RFET. c) False-colored SEM image of fabricated RFET device, based on 60 nm wide nanochannel. d) Schematic band diagrams of the most relevant operation modes of a Three-Gated RFET: off-states for both lowVT and highVT modes are shown, together with the on-state, which is the same for both operations. e) Table summarizing the possible RFET operations: the highlighted ones will be analyzed in this paper. f) Three-Gated RFET fabrication process flow. g) Ambipolar transfer curves for p/n-type branches, obtained on a different set of devices: the shaded area around the solid line (mean) shows the standard deviation calculated on 50 measured devices. h,i) P-type and n-type transfer curves of the lowVT mode for different values of the drain voltage. l,m) P-type and n-type transfer curves of the lowVT mode for different values of the program voltage. In m) it is possible to observe a shift in the VT when the device is programmed at 1 V: this non-ideality is probably due to traps generated in the gate oxide during measurement. 

Acknowledgements: This work was supported in part by the State budget by the delegates of the Saxon State Parliament and in part by the German Research Foundation (DFG) within the projects number 326384402 and SPP2253 under project number 439891087. 

[paper] Noise Characterization of MOSFETs for Cryogenic Electronics

Variable-Temperature Broadband Noise Characterization of MOSFETs

for Cryogenic Electronics: From Room Temperature down to 3K

Kenji Ohmori¹ and Shuhei Amakawa²

TechRxiv. DETM 2022 Preprint

DOI: 10.36227/techrxiv.21762917.v1

1 Device Lab Inc., Tsukuba, Ibaraki, Japan,

2 Hiroshima University, Higashihiroshima, Hiroshima, Japan

Abstract: A broadband noise measurement system is newly developed and demonstrated at temperatures between 3K and 300K. Using the system, wideband noise spectroscopy (WBNS) from 20kHz to 500MHz is carried out for the first time, revealing that shot noise is the dominant white noise down to 3K. The paper also suggests, by means of WBNS, the possibility of extracting the baseline noise characteristics, which do not include the noise component that varies a great deal from device to device.

FIG: a.) IdVg Curves at T = 2.9K ... 300K and b.) 1/f Noise at T=5K

Acknowledgement: 

This work was partially supported by NEDO-SBIR.

[paper] Cryogenic Temperature Effects in 10-nm Bulk CMOS FinFETs

Sujit K. Singh, Sumreti Gupta, Reinaldo A. Vega* and Abhisek Dixit

Accurate Modeling of Cryogenic Temperature Effects in 10-nm Bulk CMOS FinFETs Using the BSIM-CMG Model

in IEEE Electron Device Letters

DOI: 10.1109/LED.2022.3158495.

  

 Indian Institute of Technology, New Delhi (IN)

*IBM Research, Albany, NY (USA)

Abstract: In this letter, we have proposed modifications to the existing BSIM-CMG compact model to enhance its ability to model the behavior of short channel bulk FinFETs (both n and p-type) from room temperature down to cryogenic temperatures (10K). The proposed model is highly accurate in capturing the subthreshold swing, threshold voltage, and effective mobility trends observed in FinFET cryogenic operation. For efficient optimization of the proposed model parameters, we have proposed an adequate modeling strategy. We have compared convergence time between the existing BSIM-CMG model and the proposed model by simulating a reasonably large circuit using pseudo-inverters.

Fig (a) TEM image of the fin cross-section (b) Measured device layout-related parameters 

[paper] CMOS floating-gate device for quantum control hardware

Michele Castriotta¹, Enrico Prati², Giorgio Ferrari¹

Cryogenic characterization and modeling of a CMOS floating-gate device 

for quantum control hardware

preprint arXiv:2110.02315, 2021

1 Dipartimento di Elettronica, Informazione e Bioingegneria, Politecnico di Milano (I)
2 Istituto di Fotonica e Nanotecnologie, Consiglio Nazionale delle Ricerche (I)

Abstract - We perform the characterization and modeling of a floating gate device realized with a commercial 350-nm CMOS technology at cryogenic temperature. The programmability of the device offers a solution in the realization of a precise and flexible cryogenic system for qubits control in large-scale quantum computers. The device stores onto a floating-gate node a non-volatile charge, which can be bidirectionally modified by Fowler-Nordheim tunneling and impact-ionized hot electron injection. These two injection mechanisms are characterized and modeled in compact equations both at 300 K and 15 K. At cryogenic temperature, we show a fine-tuning of the stored charge compatible with the operation of a precise analog memory. Moreover, we developed accurate simulation models of the proposed floating-gate device that set the stage for designing a programmable analog circuit with better performances and accuracy at a few Kelvin. This work offers a solution in the design of configurable analog electronics to be employed for accurately read out the qubit state at deep-cryogenic temperature.

Fig: Simplified layout of the p-type floating-gate device under test. The capacitive coupling to the floating-gate node  is realized with the poly 2 control gate.

Acknowledgments: This work was supported by QUASIX Grant from  Italian Space Agency. This work was partially performed at Polifab, the  micro- and nanofabrication facility of Politecnico di Milano