[book] Advanced Nanoscale MOSFET Architectures

Advanced Nanoscale MOSFET Architectures:

Current Trends and Future Perspectives

Kalyan Biswas, Angsuman Sarkar

John Wiley & Sons - Technology & Engineering (2024) 336 pages

ISBN: 978-1-394-18894-9

Comprehensive reference on the fundamental principles and basic physics dictating metal–oxide–semiconductor field-effect transistor (MOSFET) operation. Advanced Nanoscale MOSFET Architectures provides an in-depth review of modern metal–oxide–semiconductor field-effect transistor (MOSFET) device technologies and advancements, with information on their operation, various architectures, fabrication, materials, modeling and simulation methods, circuit applications, and other aspects related to nanoscale MOSFET technology. The text begins with an introduction to the foundational technology before moving on to describe challenges associated with the scaling of nanoscale devices. Other topics covered include device physics and operation, strain engineering for highly scaled MOSFETs, tunnel FET, graphene based field effect transistors, and more. The text also compares silicon bulk and devices, nanosheet transistors and introduces low-power circuit design using advanced MOSFETs.

Table of Contents:

[1] Emerging MOSFET Technologies; pp. 1

Kalyan Biswas and Angsuman Sarkar

[2] MOSFET: Device Physics and Operation; pp. 15

Ruthramurthy Balachandran, Savitesh M. Sharma, and Avtar Singh

[3] High-k Dielectrics in Next Generation VLSI/Mixed Signal Circuits; pp. 47

Asutosh Srivastava

[4] Consequential Effects of Trap Charges on Dielectric Defects for MU-G FET; pp. 61

Annada S. Lenka and Prasanna K. Sabu

[5] Strain Engineering for Highly Scaled MOSFETs; pp. 85

Chinmay K. Maiti, Taraprasanna Dash, Jhansirani Jena, and Eleena Mohapatra

[6] TCAD Analysis of Linearity Performance on Modified Ferroelectric Layer in FET Device with Spacer; pp. 113

Yash Pathak, Kajal Verma, Bansi Dhar Malhotra, and Rishu Chauzar

[7] Electrically Doped Nano Devices: A First Principle Paradigm; pp. 125

Debarato D. Ray, Pradipta Roy, and Debashis De

[8] Tunnel FET: Principles and Operations; pp. 143

Zahra Ahangari

[9] GaN Devices for Optoelectronics Applications; pp. 175

Nagarajan Mohankumar and Girish S. Mishra

[10] First Principles Theoretical Design on Graphene-Based Field-Effect Transistors; pp. 201

Yoshitaka Fujimoto

[11] Performance Analysis of Nanosheet Transistors for Analog ICs; pp. 221

Yogendra R Pundir, Arvind Bisht, and Pankaj K. Pal

[12] Low-Power Analog Amplifier Design using MOS Transistor in the Weak Inversion Mode; pp. 255

Soumya Pandit and Koyel Mukherjee

[13] Ultra-conductive Junctionless Tunnel FET-based Biosensor with Negative Capacitance; pp. 281

Palasri Dhar, Soumik Poddar, and Sunipa Roy

[14] Conclusion and Future Perspectives; pp. 301

Kalyan Biswas and Anqsuman Sarkar

[INDEX]; pp. 311

Workshop on Advanced Integrated Circuit Design

U.S.-Japan Collaborative Workshop on Advanced Integrated Circuit Design

(Phase 2)

Fukuoka System LSI Development Center 2F

May 14 - May 15, 2024

https://www.kerc.or.jp/seminar/2024/04/5145152.html

In recent years, R&D and investment in semiconductors have become more active in countries around the world, and at the same time, the need for human resource development has been pointed out. In Japan in particular, the construction and attraction of factories for semiconductor "manufacturing" is accelerating, and various activities are being developed, but in the future, it is necessary to accelerate discussions on semiconductor "design". Against this backdrop, with the support of the U.S. Consulate in Fukuoka, we decided to hold a workshop in collaboration with the U.S. In December 2023, we held the U.S.-Japan Collaborative Workshop on Circuit Design (Phase 1), a state-of-the-art integrated circuit design, with the aim of learning about the latest situation in both countries through lectures on cutting-edge design technology and human resource development in Japan and the United States, as well as discussing the future direction and possibilities for international collaboration. We cover a wide range of topics, including open IC design, advanced analog and digital circuit design, generative AI processing (LLM) acceleration, optical circuit design, cryogenic classical and quantum computing, and new device technologies. Hybrid format (lectures can be held at Fukuoka venues and ZOOM Webinars), free of charge, with simultaneous English-Japanese interpretation. Therefore, it is a form that is easy to participate in. This is a good opportunity to learn about global trends, so not only those who specialize in semiconductors, but also those who are even a little interested in semiconductors, please join us. Students are also welcome to participate! In addition, we plan to have a simple hands-on session in the tutorial session, so if you are interested, please bring / prepare a laptop.

Outline of the event

Date & Time

DAY-1: May 14, 2024 10:00 a.m. ~ 4:00p.m.
DAY-2: May 15, 2024 10:00 a.m. ~ 4:05 p.m.

Hybrid format (lectures can be held at Fukuoka venues and ZOOM Webinars)
Online (Zoom Webinars)

Fukuoka Venue: Fukuoka System LSI Development Center 2F
(〒814-0001 3-8-33 Momochihama, Sawara-ku, Fukuoka City)
There is no parking lot at the venue, so if you come by car, please use the
nearby paid parking lot.

Participation Fee:  free

Application
[Application deadline: May 13]
Please apply from the link below (you can also apply for either Day-1 or Day-2 only). Simultaneous interpretation in English and → is available at the Fukuoka venue and ZOOM Webinars. The first 70 people to participate at the Fukuoka venue and the first 400 people to participate in the ZOOM Webinar will be closed to the first 400 people. If you wish to cancel after applying for the Fukuoka venue, please contact us as soon as possible. In addition, we are planning a simple hands-on, so please bring your laptop (you can participate without a laptop).

Application Form

Program Details  (subject to update) https://www.kerc.or.jp/seminar/2024/04/5145152.html

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Day-1: May 14, 10:00-16:00 (JST)

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10:00 - 10:05 Opening Remark and Overview of the Workshop, Mehdi Saligane/Koji Inoue, University of Michigan/Kyushu University

[Morning Session: Invited Talks]
10:05 - 10:10 Welcome Remarks from the U.S. Consulate in Fukuoka
10:10 - 10:55 LLMs on ASICs, Greg Kielian/Kauna Lei, Google Research
11:00 - 11:45 Teaching Mixed-Signal Design Using Open-Source Tools, Boris Murmann, University of Hawaii
11:45 - 13:00 Lunch Break

[Afternoon Session: Tutorials]
13:00 - 14:00 Photonic and Analog circuits with GDSFactory, Joaquin Matres/Troy Tamas, Google X/DoPlayDo, Inc.
14:00 - 14:15 Break
14:15 - 15:45 ReaLLMASIC: Build your own Lightweight LLM, Gregory Kielian/Kauna Lei/Shiwei Liu/Mehdi Saligane, Google Research/University of Michigan
15:45 - 16:00 Conclusion, Mehdi Saligane, University of Michigan

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Day-2: May 15th, 10:00-16:05 (JST) 

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10:00 - 10:05 Opening Remark and Overview of Day-2 Workshop, Mehdi Saligane/Koji Inoue, University of Michigan/Kyushu University
[Morning Session: Invited Talks]
10:05 - 10:50 Superconductor Computer Architecture: from Classical to Quantum, Ilkwon Byun, Kyushu University
10:50 - 11:35 Overview of new devices in the era of Beyond CMOS, Sadayuki Yoshitomi, Megachips
11:35 - 13:00 Lunch Break
[Afternoon Session: Tutorials]
13:00 - 13:55 (Tentative: GLayout), Anhang Li/Boris Murmann/Mehdi Saligane, University of Michigan/University of Hawaii
13:55 - 14:50 (Tentative: XLS: High-Level Synthesis), Johan Euphrosine, Google
14:50 - 15:05 Break
15:05 - 16:00 Pitfalls of Open-Source Chip Design Verification, Mitch Bailey, Efabless/ShuhariSystem
16:00 - 16:05 Conclusion and Overview of the phase-2 workshop activities, Mehdi Saligane/Koji Inoue, University of Michigan/Kyushu University

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Organizer

University of Michigan
Kyushu University System LSI Research Center Kyushu University
Quantum Computing Systems Research Center Kyushu University
Value Creation Semiconductor Human Resource Development Center

Co-organizers
Fukuoka Prefectural Foundation for the Promotion of Industry, Science and Technology Kyushu Economic Research Association

Sponsor
U.S. Consulate in Fukuoka

Inquiries
ic-design-ws 'at' slrc.kyushu-u.ac.jp (replace 'at' with @)
Okano, Business Development Department, TEL: 092-721-4907

[Symposium] SFRC AIST

Advanced Semiconductor Research Center (SFRC) 

National Institute of Advanced Industrial Science and Technology (AIST)

1st Open Symposium 

https://unit.aist.go.jp/sfrc/sfrcsympo202405.html

Date: May 27, 2024

Venue: Fujisoft Akiba Plaza Akiba Hall (3 Kanda-Neribaki-cho, Chiyoda-ku, Tokyo) 

Hybrid event (on-site participation and remote streaming)

AGENDA:

Moderator: Takashi Matsukawa (Deputy Director, SFRC)
13:00-13:05 Opening Remarks Tetsuji Yasuda (AIST Electronics & Manufacturing)
13:05-13:10 Guest Greetings Mr. Tsutomu Kanashi (Director, Information Industry Division, Commerce and Information Policy Bureau, Ministry of Economy, Trade and Industry)
13:10-13:40 Keynote Speech 1 "Rapidus and Advanced Semiconductor Development" Masaharu Kobayashi (Rapidus Corporation)
13:40-14:10 Keynote Speech 2 "The Current Situation and Future of the Semiconductor Industry from a Systems Perspective" Kenji Tsuda (International Technology Journalist)
14:10-14:20 "Introduction to the Advanced Semiconductor Research Center" Akiue Masahara (Director, SFRC Research Center)
14:20-14:40 "Introduction of SCR Open Pilot Line" Fuminori Ito (Deputy Director, SFRC)
14:40-14:55 "2nm Generation GAA-FET Fundamental Technology" Hisashi Irizawa (SFRC) Head, Device Process Research Team)
14:55-15:10 "Extreme Device and Material Technology for the 2nm Generation and Beyond" Naoya Okada (Head, Extreme CMOS Materials Research Team, SFRC)
15:10-15:30 Coffee Break
15:30-16:00 Keynote Speech 3 "What is Open Source Utilized Silicon Initiatives (Open-SUSI)?" Jun-Ichi Okamura (AIST Solutions)
16:00-16:15 "Device Integration Technology by 3D Integrated Packaging Technology Katsuya Kikuchi (Director, SFRC 3D Integrated Technology Research Team)
16:15-16:30 "Advanced System-on-Chip (SoC) Design Technology"
Shinichi Ouchi (AIDL Laboratory Team Leader/SFRC Integrated Circuit Design Research Team)
16:30-16:45 Environmental Impact Assessment of Semiconductor Manufacturing and Greening Technologies" Shinji Mimida (SFRC)
16:45-17:00 "Quantum-related semiconductor integrated device technology" Takahiro Mori (Director, SFRC New Principles Silicon Device Research Team)
17:00-17:15 Q&A
17:15-17:30 Closing Remarks Takashi Nakano (Deputy Director, Research Strategy Planning Department, AIST)

On-site participation, remote participation: Participation is free. (Please register for this form) Remote streaming is scheduled for Zoom. Please register one by one if you wish to participate. Please note that there is a limit to the number of participants at the venue.

Secretariat contact <https://unit.aist.go.jp/sfrc/sfrcsympo202405.html>

National Institute of Advanced Industrial Science and Technology (AIST) Advanced Semiconductor Research Center Symposium Secretariat (M-SFRC-Sympo-ml@aist.go.jp)

[book] Advanced Ultra Low-Power Semiconductor Devices

Advanced Ultra Low-Power Semiconductor Devices

Design and Applications

Edited by Shubham Tayal, Abhishek Kumar Upadhyay, Shiromani Balmukund Rahi, and Young Suh Song

ISBN: 9781394166411 | (C)2023  Hardcover | 306 pages

Description

This outstanding new volume offers a comprehensive overview of cutting-edge semiconductor components tailored for ultra-low power applications. These components, pivotal to the foundation of electronic devices, play a central role in shaping the landscape of electronics. With a focus on emerging low-power electronic devices and their application across domains like wireless communication, biosensing, and circuits, this book presents an invaluable resource for understanding this dynamic field.

Bringing together experts and researchers from various facets of the VLSI domain, the book addresses the challenges posed by advanced low-power devices. This collaborative effort aims to propel engineering innovations and refine the practical implementation of these technologies. Specific chapters delve into intricate topics such as Tunnel FET, negative capacitance FET device circuits, and advanced FETs tailored for diverse circuit applications.

Beyond device-centric discussions, the book delves into the design intricacies of low-power memory systems, the fascinating realm of neuromorphic computing, and the pivotal issue of thermal reliability. Authors provide a robust foundation in device physics and circuitry while also exploring novel materials and architectures like transistors built on pioneering channel/dielectric materials. This exploration is driven by the need to achieve both minimal power consumption and ultra-fast switching speeds, meeting the relentless demands of the semiconductor industry. The books scope encompasses concepts like MOSFET, FinFET, GAA MOSFET, the 5-nm and 7-nm technology nodes, NCFET, ferroelectric materials, subthreshold swing, high-k materials, as well as advanced and emerging materials pivotal for the semiconductor industrys future.