Hung-Chi Han1, (Student, IEEE), Zhixing Zhao2, Steffen Lehmann2,
Edoardo Charbon1, (Fellow, IEEE), and Christian Enz1 (Life Fellow, IEEE)
Novel Approach to FDSOI Threshold Voltage Model Validated at Cryogenic Temperatures
in IEEE Access, DOI: 10.1109/ACCESS.2023.3283298
1 Ecole Polytechnique Fédérale de Lausanne (EPFL), 2000 Neuchâtel, Switzerland
2 GlobalFoundries, 01109 Dresden, Germany
Abstract: The paper presents a novel approach to to the modeling of the back-gate dependence of the threshold voltage of Fully Depleted Silicon-On-Insulator (FDSOI) MOSFETs down to cryogenic temperatures by using slope factors with a gate coupling effect. The FDSOI technology is well-known for its capability to modulate the threshold voltage efficiently by the back-gate voltage. The proposed model analytically demonstrates the threshold voltage as a function of the back-gate voltage without the pre-defined threshold condition, and it requires only a calibration point, i.e., a threshold voltage with the corresponding back-gate voltage, front- and back-gate slope factors, and work functions of front and back gates. The model has been validated over a wide range of the back-gate voltages at room temperature and down to 3 K. It is suitable for optimizing low-power circuits at cryogenic temperatures for quantum computing applications
FIG: Room temperature back-gate coefficient η versus VT−VB for an n-type conventional well (RVT) FDSOI FET with 1 µm of gate length and width. The θ=0 happens at VT−VB = −0.63V due to −0.63V of the front-back gate work function difference
Acknowledgment: The authors would like to thank Claudia Kretzschmar from GlobalFoundries Germany and GlobalFoundries University Partnership Program for providing 22 FDX® test structures and support. Hung-Chi Han would like to thank Davide Braga from Fermi National Accelerator Laboratory for his valuable support. This project has received funding from the European Union’s Horizon 2020 Research & Innovation Program under grant agreement No. 871764. SEQUENCE.
