[paper] PSP RF Model

Xiaonian Liu1, 2, and Yansen Liu1, 2

Scalable PSP RF Model for 0.11 µm MOSFETs

Progress In Electromagnetics Research Letters, Vol. 113, 43–51, 2023

1 School of Physics and Electronics, Hunan Normal University, Changsha 410081, China
2 Key Laboratory of Physics and Devices in Post-Moore Era, College of Hunan Province, Changsha 410081, China.

Abstract: An accurate, efficient and scalable SPICE model is essential for modern integrated circuits design, especially for radio frequency (RF) circuit design. A PSP based scalable RF model is extracted and verified in 0.11 µm CMOS manufacturing process. The S parameter measurement system and open-short de-embedding technique is applied. The macro-model equivalent subcircuit and parameters extraction strategy are discussed. The extracted model can match the de-embedded S parameters data well. By combining the model parameters’ dependencies on each geometry quantity, the scalable expression of parameters with all geometry quantities included can be obtained. This work can be a reference for the RF MOSFETs modeling and RF circuit design.

Fig: The PSP RF subcircuit model and its S-par s fitting

results of NMOS with Wf = 2 µm, Lf = 0.12 µm, nf = 16

Acknowledgment: This work is supported by the National Natural Science Foundation of China under Grant 62204083, and the Youth Fund of Education Department of Hunan Province under Grant 21B0057.

[paper] PSP RF Model

Xiaonian Liu^{1, 2} and Yansen Liu¹

A Scalable PSP RF Model for 0.11 µm MOSFETs

Progress In Electromagnetics Research Letters, Vol. 113, 43–51, 2023

DOI :10.2528/PIERL23081405

1 School of Physics and Electronics, Hunan Normal University, Changsha 410081, China.
2 Key Laboratory of Physics and Devices in Post-Moore Era, College of Hunan Province, Changsha 410081, China.

Abstract : An accurate, efficient and scalable SPICE model is essential for modern integrated circuits design, especially for radio frequency (RF) circuit design. A PSP based scalable RF model is extracted and verified in 0.11 CMOS manufacturing process. The S parameter measurement system and open-short de-embedding technique is applied. The macro-model equivalent subcircuit and parameters extraction strategy are discussed. The extracted model can match the de-embedded S parameters data well. By combining the model parameters’ dependencies on each geometry quantity, the scalable expression of parameters with all geometry quantities included can be obtained. This work can be a reference for the RF MOSFETs modeling and RF circuit design.

Fig: The RF PSP Model Subcircuit

Acknowledgment : This work is supported by the National Natural Science Foundation of China under Grant 62204083, and the Youth Fund of Education Department of Hunan Province under Grant 21B0057.

3rd MFEM Community Workshop, October 26, 2023

MFEM is a free, open source, lightweight, scalable C++ library for finite element methods.

Features

• Arbitrary high-order finite element meshes and spaces.
• Wide variety of finite element discretization approaches.
• Conforming and nonconforming adaptive mesh refinement.
• Scalable from laptops to GPU-accelerated supercomputers.
• ... and many more.
• See MFEM Gallery, Publications, Videos and News pages.

MFEM is used in many projects, including BLAST, Cardioid, Palace, VisIt, RF-SciDAC, FASTMath, xSDK, and CEED in the Exascale Computing Project.

Annual workshop 

MFEM host an annual workshop and FEM@LLNL seminar series. The MFEM team has  announced the 3rd MFEM Community Workshop, which will take place on October 26, 2023, virtually, using Zoom for videoconferencing. The goal of the workshop is to foster collaboration among all MFEM users and developers, share the latest MFEM features with the broader community, deepen application engagements, and solicit feedback to guide future development directions for the project.

Registration
If you plan to attend, please register no later than October 19th. There is no registration fee. Zoom details will be distributed to participants prior to the event date. For questions, please contact the meeting organizers at mfem@llnl.gov.

[paper] ControlPULP: A RISC-V On-Chip Parallel Power Controller for Many-Core HPC Processors

ControlPULP: A RISC-V On-Chip Parallel Power Controller for Many-Core HPC Processors with FPGA-Based Hardware-In-The-Loop Power and Thermal Emulation

Alessandro Ottaviano1, Robert Balas1, Giovanni Bambini2, Antonio del Vecchio2, Maicol Ciani2, Davide Rossi2, Luca Benini1,2 and Andrea Bartolini2

DOI: 10.21203/rs.3.rs-2525734/v1

1 Integrated Systems Laboratory, ETH Zurich, Gloriastrasse 35, Zurich, 8092, Switzerland.
2 DEI, University of Bologna, Viale Del Risorgimento 2, Bologna, 40136, Italy

Abstract: High-Performance Computing (HPC) processors are nowadays integrated Cyber-Physical Systems demanding complex and high-bandwidth closed-loop power and thermal control strategies. To efficiently satisfy real-time multi-input multi-output (MIMO) optimal power requirements, high-end processors integrate an on-die power controller system (PCS). While traditional PCSs are based on a simple microcontroller (MCU)-class core, more scalable and flexible PCS architectures are required to support advanced MIMO control algorithms for managing the ever-increasing number of cores, power states, and process, voltage, and temperature variability. This paper presents ControlPULP, an open-source, HW/SW RISC-V parallel PCS platform consisting of a single-core MCU with fast interrupt handling coupled with a scalable multicore programmable cluster accelerator and a specialized DMA engine for the parallel acceleration of real-time power management policies. ControlPULP relies on FreeRTOS to schedule a reactive power control firmware (PCF) application layer. We demonstrate ControlPULP in a power management use-case targeting a next-generation 72-core HPC processor. We first show that the multicore cluster accelerates the PCF, achieving 4.9x speedup compared to single-core execution, enabling more advanced power management algorithms within the control hyper-period at a shallow area overhead, about 0.1% the area of a modern HPC CPU die. We then assess the PCS and PCF by designing an FPGA based, closed-loop emulation framework that leverages the heterogeneous SoCs paradigm, achieving DVFS tracking with a mean deviation within 3% the plant’s thermal design power (TDP) against a software-equivalent model-in-the-loop approach. Finally, we show that the proposed PCF compares favorably with an industry grade control algorithm under computational-intensive workloads.

• https://github.com/Arm-software/SCP-firmware
• https://github.com/open-power
• https://github.com/pulp-platform/control-pulp 
• https://github.com/openhwgroup/cv32e40p
• https://github.com/pulp-platform/clic
• https://github.com/EEESlab/examon
• https://buildroot.org/

FIG: ControlPULP hardware architecture. On the left, the manager domain with the manager core and surrounding peripherals. On the right, the cluster domain accelerator with the eight cores (workers)