Showing posts with label III-V material. Show all posts
Showing posts with label III-V material. Show all posts

Mar 19, 2024

[Habilitation] Assessment of novel devices in CMOS technology

Assessment of novel devices in CMOS technology
by electrical characterization and physics-based model
Habilitation Presented To Obtain The Authorization 
To Direct Research From Sorbonne University
Lionel Trojman, PhD
Sorbonne Université, 2020
Organization of the thesis
Chapter 1: This chapter extends research work after the author’s PhD study. It focuses on HfO2-based dielectric MOSFETs with sub-1nm EOT. The study explores the impact of transport factors like saturation velocity on planar MOSFETs and the mobility of FDSOI-UTBB MOSFETs. Notably, the back-biased effect is considered, and an inversion charge model is developed for different front and back biases.
Chapter 2: Emphasis the application of the statistical defect-centric model to assess the impact of channel hot carriers on the reliability of low-dimensional MOSFETs.
Chapter 3: This chapter shifts focus to GaN-on-Si wafer devices for power electronic applications. These devices integrate MOS-like structures into III-V material-based devices, specifically MOS-HEMT and GET-SBD.
Chapter 4: Investigates RERAM devices. It stems from cooperative research with UNICAL and a PhD program in collaboration with Aix-Marseille University

FIG: Description of the gate structure (half device) of the studied device including the parasitic capacitance inner fringing (CIF), outer fringe (COF) and Junction overlap capacitance (COV)