Showing posts with label scattering. Show all posts
Showing posts with label scattering. Show all posts

Mar 8, 2023

[paper] Cryogenic Characteristics of InGaAs MOSFET

L. Södergren, P. Olausson and E. Lind
Cryogenic Characteristics of InGaAs MOSFET
in IEEE TED, vol. 70, no. 3, pp. 1226-1230, March 2023,
DOI: 10.1109/TED.2023.3238382

Abstract: We present an investigation of the temperature dependence of the current characteristic of a long-channel InGaAs quantum well MOSFET. A model is developed, which includes the effects of band tail states, electron concentration-dependent mobility, and interface trap density to accurately explain the measured data over all modes of operation. The increased effect of remote impurity scattering is associated with mobility degradation in the subthreshold region. The device has been characterized down to 13 K, with a minimum inverse subthreshold slope of 8 mV/dec and a maximum ON-state mobility of 6700 cm2/Vs and with values of 75 mV/dec and 3000 cm2/Vs at room temperature.

FIG: Measured transfer characteristics at 13, 100, and 300 K together with the fit model with
(a) VDS=50 mV and (b) VDS=500 mV.






Mar 18, 2022

[paper] Electron Mobility Distribution in FD-SOI MOSFETs

Nima Dehdashti Akhavana, Gilberto Antonio Umana-Membrenoa, Renjie Gua, Jarek Antoszewskia, Lorenzo Faraonea and Sorin Cristoloveanub
Electron mobility distribution in FD-SOI MOSFETs using a NEGF-Poisson approach
Solid-State Electronics; Available online 14 March 2022, 108283
DOI: 10.1016/j.sse.2022.108283
   
a The University of Western Australia, Crawley (AU)
b IMEP-LAHC, INP Minatec, Grenoble (F)


Abstract: Modern electronic devices consist of several semiconductor layers, where each layer exhibits a unique carrier transport properties that can be represented by a unique mobility characteristic. To date, the mobility spectrum analysis technique is the main approach that has been developed and applied to the analysis of conductivity mechanisms of multi-carrier semiconductor structures and devices. Currently, there are no theoretical calculations of the mobility distribution in semiconductor structures or devices and specifically in MOSFET devices. In this article, we present a theoretical study of the electron mobility distribution in planar fully-depleted silicon-on-insulator (FD-SOI) transistors employing quantum mechanical modelling. The simulation results indicate that electronic transport in the 10 nm thick Si channel layer at room-temperature is due to two distinct and well-defined electron species for channel length varying from 50 nm to 200 nm. The two electron mobility distributions provide clear evidence of sub-band modulated transport in 10-nm thick Si planar FD-SOI MOSFETs that are associated with primed and non-primed valleys of silicon. The potential of the top gate electrode has been modulated, and thus only the top channel inversion-layer electron population transport parameters have been investigated employing self-consistent non-equilibrium Green’s function (NEGF)–Poisson numerical calculations. The numerical framework presented can be used to interpret experimental results obtained by magnetic-field dependent geometrical magnetoresistance measurements and mobility spectrum analysis, and provides greater insight into electron mobility distributions in nanostructured FET devices.

Fig: Qinv is defined as the electron density per unit length at the maximum 
of the first subband (top of the barrier) often referred to as a “virtual source”

Acknowledgements: This work was supported by the Australian Research Council (DP170104555), the Horizon 2020 ASCENT EU project (Access to European Nanoelectronics Network – Project no. 654384), the Western Australian node of the Australian National Fabrication Facility (ANFF), and the Western Australian Government’s Department of Jobs, Tourism, Science and Innovation.