Call for Papers
INVITED SPEAKERS
#TCAD Simulation of #Organic #Optoelectronic #Devices https://t.co/k7iZDQjppR #papers
— Wladek Grabinski (@wladek60) January 23, 2017
Swisstech Convention Centre Quartier Nord de l'EPFL Route Louis-Favre 2 CH-1024 Ecublens (CH)
The MOS-AK Association, a global compact/SPICE modeling and Verilog-A standardization forum, held its annual Q4 event on December 7, 2016 UC Berkeley as its 9th consecutive International MOS-AK Workshop. The event was coordinated by Larry Nagel, OEC (USA) and Andrei Vladimirescu, UCB (USA); ISEP (FR) representing the International MOS-AK Board of R&D Advisers. The workshop was hosted by Prof. Jaijeet Roychowdhury of EECS at the University of California at Berkeley and co-sponsored by Keysight Technologies and NEEDS of nanoHUB.org.
The workshop provided presentations from the leading developers of compact device models. The audience spanned the full range of the semiconductor industry, including representatives from foundries, model characterization services firms, academic researchers investigating emerging device technologies, and design companies. The amount and breadth of technical information discussed was vast -- here are but a few highlights by ChipGuy:| Open source software | Description | Web site |
| wol | Wol is a graphical environment for IC mask layout | http://www.cs.berkeley.edu/~lazzaro/chipmunk/describe/wol.html |
| toped | Micron based layout editor with extensive scripting capabilities. Under active development and part of Fedora Electronic Lab. | http://www.toped.org.uk |
| microwind3 | Lambda based layout editor especially adapted for interactive design with Spice. This used to be completely free, but now only a Lite version is. | http://www.microwind.org |
| magic | Lambda based layout editor with good options for writing CIF and/or GDS files. Supports scripting. Large user base. Part of Fedora Electronic Lab. Used for extraction and CIF/GDS creation by the pharosc libraries |
http://opencircuitdesign.com/magic |
| lasi | LASI stands for LAyout Software for Individuals. It is designed to run on Windows, though it also runs on Linux under Crossover Office. Actively used software with frequent updates. |
http://lasihomesite.com |
| kic | Part of open source packages released by Whiteley Research. | http://wrcad.com/freestuff.html |
| graal | Lambda based layout editor allowing conversion to CIF and GDS with appropriate technology files. Dreal is the companion software to view CIF and GDS. Part of a tool set from Alliance which is probably the best open-source software for IC design. Comes with own standard cell library. Part of Fedora Electronic Lab. The pharosc standard cells are drawn with graal. |
http://www-asim.lip6.fr/recherche/alliance |
| electric | Comprehensive set of software programs designed around the concept of silicon compilation. Version 6 crashed a lot, and stored all design data in a single file which exposed one to the risk of file corruption and loss of all data (I speak from experience). New version written in Java. Extensive documentation. |
http://www.staticfreesoft.com/productsSoftware.html |
| dreal | Simple layout editor which uses CIF or GDS as its native format. Companion software is Graal. | http://www-asim.lip6.fr/recherche/alliance |
| Cheap software | ||
| xic | Whiteley Research Inc. Layout editor with linked Spice simulator. List price is $1195. | http://www.wrcad.com/xic.html |
| slam-edit | Stabie-Soft Inc. Unix/Linux based layout editor. It seems a licence cannot be purchsed, only leased for one year periods (bad if the company folds). List price on web site is $2,000 per year. | http://www.stabie-soft.com/sledit.html |
| ledit | Tanner Research Inc. Windows only layout editor popular with mixed signal designers. Ledit sed to cost $1,000, but this price could not be verified (which is surprising since low price is a key selling point of the software). | http://www.tanner.com/EDA/product/Tools_PhysicalLayout.html |
| layedpro | Mycad Inc. Windows only layout editor designed in Korea but supported for English language users from California. No new product since 2005 on US site, but Korean site seems active. No price could be confirmed. | http://www.mycad.com/02pro/01.html http://www.mycad.co.kr |
| layed | Catena Software GmbH. Demo versions for Linux and Windows can be downloaded. List price of the basic editor might be €1,585 (could not be recently verified). | http://www.catena-ffo.de/laytools.htm |
| iced | IC Editors Inc. Windows only editor that used to cost $2,750. Now it is free but with a restrictive licence. Work is on-going to open source it which might make it available under Linux (although the Windows drawing primitives would need to be replaced with GTK). | http://www.iceditors.com |
| Expensive software | ||
| virtuoso | Cadence Design Systems, Inc. The market leader. The price might be $40,000 to lease for one year. | http://www.cadence.com/products/custom_ic/veditor/index.aspx |
| max | Micro Magic Inc. Looks like a commercial version of Magic. Price is $30,000 for a one year licence. Despite the fancy price tag, something was freely downloadable from the web in the 2004 timeframe. | http://www.micromagic.com |
| laker | Silicon Canvas Inc. Linux and Unix based editor. Top of the line laker-ddl is $70,000 for a one year licence. Regular Laker 3 is $35,000 for a one year licence. | http://www.sicanvas.com |
| icstation | Mentor Graphics Corp. No public pricing information could be found. | http://www.mentor.com/cicd/icstation.html |
Ken Shirriff Takes Us Inside the IC, For Fun https://t.co/QScTdhgFXV #papers
— Wladek Grabinski (@wladek60) December 27, 2016
J-EDS Comes of Age https://t.co/4HNl9cQhzh #papers
— Wladek Grabinski (@wladek60) December 27, 2016
Special Issue of Solid-State Electronics, dedicated to EUROSOI-ULIS 2016 https://t.co/fFD9GehZEP #papers #feedly
— Wladek Grabinski (@wladek60) December 25, 2016
Top #opensource #conference picks for #2017 https://t.co/nJzg2bSbpq #papers
— Wladek Grabinski (@wladek60) December 14, 2016

The #efabless $15,000 #Design #Challenge https://t.co/OV5sjnfSxm #papers
— Wladek Grabinski (@wladek60) November 30, 2016
Investigation of Gate Direct-Current and Fluctuations in Organic p-Type Thin-Film Transistors #papers https://t.co/IS3MAiWqZY
— Wladek Grabinski (@wladek60) November 29, 2016
#Opensource #lab-on-a-board costs $29 https://t.co/cJIQPpDgvG #software #feedly #papers
— Wladek Grabinski (@wladek60) November 26, 2016
Creating A PCB In Everything: KiCad, Part 1 https://t.co/gSqz7GGbnE #todo #feedly #papers
— Wladek Grabinski (@wladek60) November 17, 2016
540 Cory Hall
EECS Department
University of California, Berkeley
Directions to the DOP Center in Cory Hall
See also http://www.eecs.berkeley.edu/Directions/
The MOS-AK Modeling Working Group, a global compact/SPICE modeling and Verilog-A standardization forum, held its annual autumn workshop on September 12, 2016 in Lausanne (CH) as its 14th consecutive modeling event at the ESSDERC/ESSCIRC Conference. The event was coordinated by Larry Nagel, OEC (USA) and Andrei Vladimirescu, UCB (USA); ISEP (FR) representing the International MOS-AK Board of R&D Advisers. The workshop was co-sponsored by ASCENT Network (lead sponsor) and EPFL EDLab, with technical program sponsorship provided by the IEEE WiE Group (CH), Eurotraining and NEEDS of nanoHUB.org.
A group of the international academic researchers and modeling engineers attended 12 technical compact modeling presentations covering full development chain form the nanoscaled technologies thru semiconductor devices modeling to advanced IC design support. The MOS-AK speakers have shared their latest perspectives on compact/SPICE modeling and Verilog-A standardization in the dynamically evolving semiconductor industry and academic R&D.
The workshop was opened by Prof. J. Greer; Tyndall National Institute, the MOS-AK keynote speaker, who has introduced the ASCENT Network. The ASCENT is combined resources of Tyndall (Ireland), imec (Belgium) and Leti (France) nanofabrication capabilities and electrical characterization facilities integrated into a single research infrastructure present a truly unique R&D opportunity. It provides characterization community with access to advanced test chips, flexible fabrication and advanced test and characterization equipment to accelerate development of advanced models at scales of 14nm and below.
The event featured additional technical presentations covering compact model development, implementation, deployment and standardization. These contributions were delivered by leading academic and industrial experts, including: Denis Rideau; STM (F), presenting a modeling study of the drain current in advanced MOSFETs. Maria-Alexandra Paun; EPFL (CH), focusing on the humidity sensors based on MWCNTs/MMA composite in SOI CMOS technological process. Mike Brinson; London Met (UK), presenting QUCS-S - maturing GPL software package for circuit simulation and compact modeling of current and emerging technology devices. Alexander Kloes; THM Giessen (D), discussing a closed-form charge-based current model of organic TFT including non-linear injection effects. Jean-Michel Sallese; EPFL (CH), discussing an advances in analytical modeling. Marco Bellini, ABB CRC (CH), presenting extraction of compact models for EMI / EMC simulations of power devices. Muhammad Nawaz; ABB CRC (S), reviewed characterization and modeling of SiC MOSFET power modules. Mansun Chan; HKUST (HK), discussing concurrent device and circuit reliability simulation. Benjamin Iñiguez; URV (SP), talking about temperature dependent GIZO TFT modeling. Mike Schwarz; THM (D), discussing analytical III-V SB MOSFET modeling and its performance analysis from room to cryogenic temperature. Matthias Bucher; TUC (GR), giving an EKV3 model update. The presentations are available online for download at http://www.mos-ak.org/
The MOS-AK Modeling Working Group has various deliverables and initiatives including a book entitled "Open Source CAD Tools for Compact Modeling" and an open Verilog-A directory with models and supporting CAD software. The MOS-AK Association plans to continue its standardization efforts by organizing additional compact modeling meetings, workshops and courses in Europe, USA, India and China throughout 2016/2017 including:
* 9th International MOS-AK Workshop at Berkeley in the timeframe of IEDM and CMC meetings (Dec.7, 2016)
* Spring MOS-AK Workshop in Lausanne during DATE Conference (March 31 2017)
* 2nd Sino MOS-AK Workshop in Hangzhou (June 2017)
* 15th MOS-AK ESSDERC/ESSCIRC Workshop in Leuven (Sept.11, 2017)
About MOS-AK Association:
MOS-AK, an international compact modeling association primarily focused in Europe, to enable international compact modeling R&D exchange in the North/Latin Americas, EMEA and Asia/Pacific Regions. The MOS-AK Modeling Working Group plays a central role in developing a common language among foundries, CAD vendors, IC designers and model developers by contributing and promoting different elements of compact/SPICE modeling and its Verilog-A standardization and related CAD/EDA tools for the compact models development, validation/implementation and distribution.
About ASCENT Network:
ASCENT provides fast and easy access to the world's most advanced CMOS technologies and infrastructure including access to 14nm CMOS device data, nanoscale test chips and device characterisation facilities at Tyndall (Ireland), imec (Belgium) and Leti (France). ASCENT has received funding from the European Union's Horizon 2020 research and innovation programme under grant agreement No 654384.2017 1st Electron Devices Technology and Manufacturing Conference (call for #papers) https://t.co/CAj9B5ifWU
— Wladek Grabinski (@wladek60) October 27, 2016
ARM Fellow Surveys Moore's Law at 3nm IC https://t.co/JUPsAtrkFb #papers— Wladek Grabinski (@wladek60) October 27, 2016
[JEDS #papers ] Characterization of RF Noise in UTBB FD-SOI MOSFET https://t.co/LNlvvNOb5V https://t.co/XQsatKslTX
— Wladek Grabinski (@wladek60) October 26, 2016
[JEDS #papers ] Characterization of RF Noise in UTBB FD-SOI MOSFET https://t.co/LNlvvNOb5V
— Wladek Grabinski (@wladek60) October 26, 2016
Transistor Sizing for Bias-Stress Instability Compensation in Inkjet-Printed Organic C-Inverters https://t.co/91uJURy3KA #papers
— Wladek Grabinski (@wladek60) October 25, 2016
| Tapeout Month |
Technology | Metal Stack | I/O | Price/mm2 | Minimum Area |
Final GDSII Due |
Tapeout Date |
Estimated Ship Date |
| October | 65nm MS RF GP | 1P9M_6x1z1u | 2.5V | $4,700 | 1mm2 | October 10 | October 12 | November 23 |
| 65nm MS RF LP | 1P9M_6x1z1u | 2.5V | $4,700 | 1mm2 | October 10 | October 12 | November 23 | |
| 180nm MS RF G | 1P6M_4x1u | 3.3V | $1,000 | 5mm2 | October 24 | October 26 | December 7 | |
| November | 40nm MS RF LP | 1P10M | 1.8V | $7,500 | 1mm2 | October 31 | November 2 | January 17 |