Showing posts with label BiCMOS. Show all posts
Showing posts with label BiCMOS. Show all posts

May 11, 2023

OpenPDK Networking Workshop


OpenPDK, OpenTooling and Open Source Design
An Initiative to Push Development
Date:
Networking Workshop FMD-QNC on 27-28 June 2023
Location:
IHP; Im Technologiepark 25; 15236 Frankfurt (Oder)
Contact:
Sergei Andreev; Phone: +49 335 5625 523
Free Registration: 




The workshop is organised by IHP and FMD (Research Fab Microelectronics Germany) within the framework of the FMD-QNC Project.

Within the project FMD-QNC analog circuit design with open source software shall be enabled. For this purpose, both the open source design tools and a process design kit of the semiconductor technology used must support the entire design flow with sufficient quality. IHP provides its 130 nm BiCMOS technology SG13G2 for open source design. This technology is particularly suited for high frequency and mixed signal design applications. While basic tool support already exists for digital circuit design, it is still very rudimentary for analog designs and especially for high frequency designs. A considerable effort has to be put into the development of the design tools as well as into the creation of the technology specific Process Design Kit (PDK).

The 2-day workshop is intended to promote exchange and networking between tool developers, the PDK developers at IHP and designers. Tool developers are to present the capabilities of the tools as well as planned enhancements. Designers are to present ideas that can be used for training chip designers. Requirements for open source design tools for digital design, mixed signal design, and high frequency design are to be highlighted.

Discussions will identify and prioritize gaps for a complete design flow in the open source tools and PDK. The workshop will thus help to concrete the planning for the Open Design Platform and to create a roadmap for future work.

Presentation

Presenter/Institution

Timeline

Day 1

Welcome by coordinator FMD-QNC

Dr. Andreas Bruning
Research Fab Microelectronics Germany

9:00-9:10

Introduction FMD-QNC project status and IHP OpenPDK Roadmap

Dr. Rene Scholz
IHP

9:10-9:30

Status OpenPDK and OpenTooling for SG13G2 BiCMOS technology

Sergei Andreev
IHP

9:30-10:00

An Ultra-Low-Power High-Density Wireless Biomedical Sensing System

 

Prof. Harald Pretl
Johannes Kepler University Linz

10:00-10:30

Teaching digital design by using open-source EDA tools

Prof. Steffen Reith
Rhein Main University of Applied Sciences

10:30-11:00

Coffee break

11:00-11:40

CMOS Rail-to-Rail Operational Amplifier for HPGe Radiation Detector

Prof. Herman Jalli Ng
Karlsruhe University of Applied Sciences

11:40-12:10

Design-flow approaches for mmWave and sub-THz integrated transceiver circuits for radar and communication

Sasha Breun
FAU Erlangen

 

12:10-12:40

Lunch break 

12:40-13:40

TBD

Dr. Frank K. Gurkaynak
ETH Zurich

13:40-14:10

TBD

Joachim Hebeler
Karlsruhe Institute of Technology

14:10-14:40

Coffee break

14:40-15:10

 TBD

Prof.  Dietmar Kissinger
Ulm University

15:10-15:40

LibMan - an easy way to manage your open source design flow

Dr. Anton Datsuk
IHP

15:40-16:10

Get together (Barbecue)

 

17:00-…

Day 2

ngspice - status and future developments

Prof. Holger Vogt

9:00-9:20

DMT - Python Toolkit for Device Modeling

Mario Krattenmacher
SemiMod

9:20-9:40

OpenVAF - Next Generation Verilog-A Compiler with ngspice integration

Mario Krattenmacher
SemiMod

9:40-10:00

Coffee break

10:00-10:40

Best practices for implementing and optimizing KLayout DRC and LVS decks

Matthias Köfferlein


10:40-11:00

Generating DRC and LVS Runsets for KLayout

Dr. Andreas Krinke
TU Dresden

11:00-11:20

OpenEMS in open source EDA

Jan Taro Svejda
University of Duisburg-Essen

11:20-11:40

Lunch break

11:40-12:40

Panel discussion on the roadmap – open source tools for IC design

Topics:

  • Digital design flow
  • Analog design flow
  • Challenges in RF design

Dr. Norbert Herfurth
IHP

Panelists: TBD

12:40-14:10

Mar 6, 2023

[open position] IHP Research Associate for Open PDK Development

Research Associate for Open PDK Development (m/f/d)
Developer for Open Source Process Design Kits
for SiGe-BiCMOS Technology
Job-ID: 7011/23 | Department: Technology | Salary: as per tariff TV-L | Working time: 40h/week (part-time work option) | Limitation: initially 2 years with option of extension for three more years | Entry Date: as soon as possible

IHP is an institute of the Leibniz Association and conducts research and development of silicon-based systems and ultra-high-frequency circuits and technologies, including new materials. It develops innovative solutions for application areas such as wireless and broadband communication, security, medical technology, industry 4.0, automotive industry, and aerospace. IHP employs approximately 350 people. It operates a pilot line for technological developments and the preparation of high-speed circuits with 0.13/0.25 µm-SiGe-BiCMOS technologies, located in a 1500 m² cleanroom that meets the highest industrial nanotechnology requirements.

The position:
As a member of the group Research & Prototyping Service, you will develop Process Design Kit for IHP’s BiCMOS technologies and new future technology modules with special focus on open source PDK development. Your detailed tasks will include programming of pCells and their integration into our verification process. Devices descriptions, user guides and test cases are important aspects of your work, too. Finally, managing our PDK repositories on Github with external contributions and adaption of existing tools like OpenRAM is part of the work. Implementation of new devices and investigations of new design tools and flows will give this position room for interesting development opportunities.

Your profile:
You hold a Master's degree in computer science with background in semiconductors, physics or electrical engineering. Knowledge in semiconductor devices and programming are of advantage. Your specialized knowledge preferably covers ASIC design environment like Cadence Virtuoso, Mentor/Siemens Tanner or KeySight ADS, OpenROAD/OpenLane, Linux and scripting languages (e.g. Python, Perl or TCL). You are well organized and always keep the overview even with many parallel projects. Thanks to your skillful communication, you are a binding and reliable contact person for our partners. You are also a strong team player, and you confidently handle the German and English language. You are also a strong team player. We are looking for a team member, who is able to structure his or her own work and to bring a well-organized and systematic way of working into the cooperation with creative minds. You are an ideal match for this position, when you have experimental, analytical and problem-solving skills, very strong communicative skills and the ability to quickly learn how to operate the latest technical equipment including various software. It is necessary that you confidently handle the English language. Knowledge of the German language is welcome. The consolidating of German language skills is expected and highly encouraged, for example in in-house language courses and intensive courses.

Your application:
Have we sparked your interest? Then we look forward to receiving your application via our online application form. For further information regarding the position, please contact Dr. René Scholz


Dec 1, 2020

[paper] THz characterization and modeling of SiGe HBTs

Sebastien Fregonese, Marina Deng, IEEE member, Marco Cabbia, Chandan Yadav*, IEEE member, Magali De Matos, and Thomas Zimmer, Senior Member, IEEE
THz characterization and modeling of SiGe HBTs
review (invited)
IEEE J-EDS, 2020, pp.1-1 
DOI:10.1109/JEDS.2020.3036135
hal-03014869

IMS Laboratory, University of Bordeaux (F)
*Department of Electronics and Communication Engineering, National Institute of Technology Calicut (IN)


Abstract: This paper presents a state-of-art review of on-wafer S-parameter characterization of THz silicon transistors for compact modelling purpose. After, a brief review of calibration/deembedding techniques, the paper focuses on the on-wafer calibration techniques and especially on the design and dimensions of lines built on advanced silicon technologies. Other information such as the pad geometry, the ground plane and the floorplan of the devices under test are also compared. The influence of RF probe geometry on the coupling with the substrate and adjacent structures is also considered to evaluate the accuracy of the measurement, especially using EM simulation methodology. Finally, the importance of measuring above 110 GHz is demonstrated for SiGe HBT parameter extraction. The validation of the compact model is confirmed thanks to an EM-spice cosimulation that integrates the whole calibration cum deembedding procedure.
Fig: EM probe models based on Picoprobe GGB (a) 1 GHz -110 GHz, (b) WR5, (c) WR3 and d) WR2.2. In all models, white=coaxial insulator, gray=solder, yellow=metal.

A complete description of probe topology and technology is given in:
A. Rumiantsev et R. Doerner; RF Probe Technology: History and Selected Topics; IEEE Microw. Mag., vol. 14, no 7, p. 46‑58, Nov. 2013, DOI: 10.1109/MMM.2013.2280241

Aknowledgement: This work is partly funded by the French Nouvelle-Aquitaine Authorities through the FAST project. The authors also acknowledge financial support from the EU under Project Taranto (No. 737454). The authors would like to thank STM for supplying the silicon wafer.


Oct 27, 2016

AMS Multi Project Wafer Service

AMS MPW Service:

ams' Multi Project Wafer (MPW) service, also known as shuttle runs, is a fast and cost-efficient prototyping service, which combines several designs from different customers onto a single wafer.

ams’ best in class MPW service offers significant cost advantages for foundry customers as the costs for wafers and masks are shared among a number of different shuttle participants. It includes the whole range of 0.18µm and 0.35µm specialty processes:
  • CMOS Mixed Signal
  • CMOS Mixed Signal with embedded EEPROM
  • CMOS High Voltage (up to 120 Volts)
  • CMOS High Voltage with embedded EEPROM
  • CMOS Opto
  • SiGe-BiCMOS
The complete MPW schedule including detailed start dates per process is available on the web at http://asic.ams.com/MPW

Deliverables: Participating the ams MPW service includes the delivery of 40 prototypes for design verification. Packaged engineering samples are offered within 2 days (ceramic) and 3 weeks (plastics) cycle time, respectively. The total turnaround time from MPW deadline to delivery is app. 8 weeks (CMOS). Overall, ams offers almost 150 MPW start dates in 2016 and 2017, enabled by long lasting co-operations with partner organizations such as CMP, Europractice, Fraunhofer IIS and Mosis. Customers located in APAC region may also participate via our local MPW program partners Toppan Technical Design Center Co., Ltd (TDC) and MEDs Technologies [read more...]

Sep 2, 2012

CMRF Workshop (at BCTM)


CMRF Workshop (at BCTM)
Wednesday October 3, 2012, in Portland, Oregon, USA

Session Chair: Colin McAndrew
As with previous years the Workshop on Compact Modeling for RF/Microwave Applications (CMRF) is being held in conjunction with BCTM. The workshop has an interactive dynamic, and this year includes a Forum of experts who will assess the present major needs in modeling.

1:00–1:30 PM – Advanced SiGe HBT Modeling with HICUM Level 0 (v1.3) for RF and mmW Applications
D. Celi and N. Derrier
This presentation deals with advanced bipolar modeling using the latest revision of HICUM/L0 (1.3). Following an overview of test structures and measurement setup used for bipolar transistors, the new HICUM/L0 formulations are described. Subsequently a workflow for parameter extraction is detailed that is suitable for advanced SiGe heterojunction bipolar transistors for mmW applications. As a last point the possibilities and limitations of the model and the parameter extraction are discussed.

1:30–2:00 PM – Dynamic Ageing Modeling for Reliability Simulation
B. Ardouin
Semiconductor device behavior is not static but changes over time, and the amount of change depends on details of the voltages and currents a device experiences. This presentation will review recent development of a dynamic ageing model for HiCuM 2.3 and provides details of Verilog-A implementation and pragmatic modeling issues related to self-consistent integration of transistor degradation in accelerated time based on realistic transient circuit operation.

2:00–2:30 PM – End-to-End Modeling for Handset Power Amplifiers – It’s Not Just Two Transistors!
P. Zampardi, Y. Yang, K. Kwok, B. Li, A. Metzger, C. Cismaru, H. Shao, W. Sun, and M. Fredriksson
The short design cycle for handset power amplifiers relies on accurate models for ALL components used in the design, not just the “two HBTs” used for the power transistors. As the complexity of these amplifiers (usually used in front-end modules) has increased, so has the required accuracy for simulating the package, control circuitry, and the RF chain itself. This presentation will show some of the challenges and solutions developed to address the development of high-yield commercial power amplifiers and the design flow for their realization.

2:50–3:20 PM – Practical Modeling: When Less is More
A. DiVergilio
The primary goal of compact modeling is to allow designs to be carried out quickly and efficiently. Therefore, model accuracy is not the only metric of model effectiveness. No matter what the circuit, significant portions of the design cycle can benefit more from rapid iteration than from absolute accuracy. Overly-complicated models slow down simulation and, at worst, prevent convergence all-together, especially for large designs. This presentation discusses trade-offs that can be made between speed and accuracy, emphasizing the flexibility that can be achieved through high-level modeling languages, such as Verilog-A, when applied to device-level model development.

3:20–4:20 PM – Forum: “Grand Challenges in Modeling”
Queen Marie Ballroom
Models are by definition imperfect, but what are the biggest opportunities for improvement that will have the biggest bang-for-the-buck in design? This forum will attempt to answer that question, and formulate a prioritized list of items that will be published on the BCTM web site.

Participants:

  • Bertrand Ardouin (XMOD technologies)
  • Adam DiVergilio (Tektronix)
  • Mikhail Shirokov (Triquint Semiconductor)
  • Peter Zampardi (Skyworks Solutions)
  • Colin McAndrew (Moderator; Freescale)

Jan 24, 2010

ISSCC 2010 Preview: Assessing '05 predictions

A couple of safe ISSCC'05 bets reviewd by Don Scansen. Have ISSCC organizers learned something by looking back?

Apr 17, 2009

CMOS vs. Bipolar Operational Amplifiers: Which is best for my application?

CMOS, bipolar or even BiCMOS are common process technologies used for the development of operational amplifiers, and each of these process technologies offers their own advantages and disadvantages when it comes to op amp design. Which one’s the best in terms of:
  • Power Consumption
  • Voltage Offset
  • Noise Performance
>>> Read further

Mar 30, 2009

after Analogschaltungen'09 in Hannover

The workshop program included following topics:
  • Novel CMOS/BiCMOS circuit architectures for the GHz range applications
  • Models of semiconductor devices for analog/RF (GHz range) applications
  • Influences of the system design and optimization on the components in the analog circuit applications
  • Classical and quantum mechanical effects in analog/RF nano-silicon circuits at GHz frequencies
The workshop has been organized by:
  • Prof. Dr. -Ing. Wolfgang Mathis, Leibniz Universität Hannover, Institut für Theoretische Elektrotechnik; Appelstr. 9A, 30167 Hannover
in cooperation with:
  • Prof. Dr.rer. nat. Doris Schmitt- Landsiedel, TU München; Lehrstuhl für Technische Elektronik
  • Prof. Dr. -Ing. Heinrich Klar, TU Berlin; Institut für Technische Informatik und Mikroelektronik
  • Prof. Dr.-Ing. Y. Manoli, Universität Freiburg; IMTEK