[paper] Degradations in LDMOS Transistors

Yen-Pu Chen¹, Bikram K. Mahajan¹, Dhanoop Varghese², Srikanth Krishnan², Vijay Reddy²

and Muhammad A. Alam¹

Three-point I–V spectroscopy deconvolves region-specific degradations in LDMOS transistors

Appl. Phys. Lett. 119, 122102 (2021); 

DOI: 10.1063/5.0058477

1 Department of ECE, Purdue University, West Lafayette, Indiana 47906, USA
2 Texas Instruments Inc., Dallas, Texas 75043, USA

Abstract: Unlike traditional logic transistors, hot carrier degradation (HCD) in power transistors involves simultaneous and potentially correlated degradation in multiple regions. One must deconvolve and characterize the voltage- and temperature-dependence of these region-specific degradations to develop a predictive HCD model of power transistors. Unfortunately, power transistors' doping and geometrical complexities make it challenging to use traditional defect-profiling techniques, such as charge-pumping or gated-diode methods. This Letter uses a physics-based tandem-FET model of Laterally Diffused MOS (LDMOS) transistors to develop a “three-point I–V spectroscopy” technique that uses the time-evolution of three critical points of the measured I–V characteristics to extract mobility and threshold voltage degradations in the channel and drift regions. This innovative approach should generalize to other configurations of the LDMOS transistor as well.

Fig: The proposed tandem-FET compact model. The channel (ch) and the drift (dr) regions function individually as a MOSFET with different 𝑉th and dimensions. Three adjustable degradation parameters are 𝛥𝜇𝑐ℎ, 𝛥𝑉𝑐ℎth, and 𝛥𝜇𝑑𝑟.

Acknowledgements: Y.-P.C and B.K.M contributed equally to this work. The authors gratefully acknowledge the access to the characterization facilities at Birck Nanotechnology Center, Purdue University, for the results presented in this article.

[paper] Compact Modeling of Flicker Noise in HV MOSFETs

Ravi Goel (Student Member, IEEE), Yogesh Singh Chauhan (Fellow, IEEE) 

Compact Modeling of Flicker Noise in High Voltage MOSFETs and Experimental Validation 

In 2021 IEEE Latin America Electron Devices Conference (LAEDC), pp. 1-4. IEEE, 2021 

DOI: 10.1109/LAEDC51812.2021.9437922

*Department of Electrical Engineering, Indian Institute of Technology Kanpur, India

Abstract: An analytical model of flicker noise (also called 1/f or low frequency noise) for the drift region is developed to formulate a 1/f model for high voltage MOSFETs using the subcircuit approach in this work. For halo doped drain extended MOSFET (DEMOS), the contribution factors of halo, channel and drift regions are obtained to capture anomalous behavior of 1/f noise. Similar to Halo doped DEMOS, for LDMOS, the contribution factors for channel and the drift region are obtained to capture the SID for different drain biases and channel lengths. The proposed model is validated with measurement data of 50V LDMOS and DEMOS.

Fig: Halo doped DEMOS and its sub-circuit equivalent. In halo doped DEMOS, the channel is divided into halo region and channel region, followed by drift region. In LDMOS, the channel is followed by the drift region. CFsh, CFch, and CFdrift are the contribution factors and are calculated using small-signal analysis.

Acknowledgments: The authors thank Sarvesh S. Chauhan for his valuable feedback. This work was partially supported by the Swarna Jayanti Fellowship (Grant No. – DST/SJF/ETA-02/2017- 18) and FIST Scheme (Grant No. – SR/FST/ETII-072/2016) of the Department of Science and Technology, India and Berkeley Device Modeling Center (BDMC).

[Survey] Power Amplifiers Performance 2000-Present

Fifth web release on 2020/10/15: "PA_Survey_v5". This version-5 dataset includes PAs/transmitters from 500MHz to 1.5 THz in Bulk/SOI CMOS, SiGe, LDMOS, InP, GaN, GaAs technologies. The dataset contains total 3207 data points with over 1200 data points for CMOS, SiGe PAs and over 1500 data points for GaN, GaAs, InP PAs.

We have added sub-THz/THz power/signal generation circuits from 15GHz to 1.5THz, including PAs, fundamenal/harmonic oscillators, and frequency multipliers, to support the emerging research on beyond-5G/6G applications.

The file "PA_Survey_v5" is the version-5 dataset that includes ALL the reported PA/transmitter data since 2000 over frequency and various technologies. It also includes summary plots on CW Psat vs. Carrier Frequency for different technologies, peak PAE vs. CW Psat at different frequencies, and average PAE vs. average Pout for high-order complex modulations.

What is new in version-5 release beyond the version-4 release? 500MHz to 1.5 THz Power Amplifier designs and sub-THz/THz power/signal generation circuits published between 02/2020 and 10/2020.

• Cite this PA survey: Hua Wang, Tzu-Yuan Huang, Naga Sasikanth Mannem, Jeongseok Lee, Edgar Garay, David Munzer, Edward Liu, Yuqi Liu, Bryan Lin, Mohamed Eleraky, Sensen Li, Fei Wang, Amr S. Ahmed, Christopher Snyder, Sanghoon Lee, Huy Thong Nguyen, and Michael Edward Duffy Smith, "Power Amplifiers Performance Survey 2000-Present," [Online]. Available: https://gems.ece.gatech.edu/PA_survey.html
• Acknowledgement: We would like to sincerely thank many of our friends and colleagues for their helpful suggestions and insightful discussions.
• Feedback and Suggestions: We welcome your feedback and suggestions, including the ways to interpret and present the data. In addition, although we try to be as inclusive as possible when collecting these published data, it is certainly possible that we may miss some representative PA designs. Please feel free to send us feedback, suggestions, or missing PA papers.
• Contact: Please contact us through poweramplifiers.survey at gmail dot com. Do not use my gatech email address, since I may very likely miss your email.
• Source for this data collection: We focus on peer-reviewed and publicly accessible publications that are typical forums for PAs, including IEEE ISSCC, JSSC, RFIC, VLSI, CICC, ESSCIRC, IMS, T-MTT, TCAS, BCTM/CSICS (BCICTS in the future), APMC, EuMC, and MWCL. We also focus on public product datasheets on PAs/transmitters.

 

 

[paper] BSIM-HV: High-Voltage MOSFET Model

H. Agarwal , Member, IEEE, C. Gupta , Graduate Student Member, IEEE, R. Goel , Graduate Student Member, IEEE, P. Kushwaha , Member, IEEE, Y.-K. Lin , Graduate Student Member, IEEE, M.-Y. Kao , Graduate Student Member, IEEE, J.-P. Duarte , Graduate Student Member, IEEE, H.-L. Chang , Member, IEEE, Y. S. Chauhan , Senior Member, IEEE, S. Salahuddin, Fellow, IEEE, and C. Hu, Life Fellow, IEEE

BSIM-HV: High-Voltage MOSFET Model Including Quasi-Saturation and Self-Heating Effect

IEEE TED, vol. 66, no. 10, pp. 4258-4263, Oct. 2019

doi: 10.1109/TED.2019.2933611

Abstract - A BSIM-based compact model for a high-voltage MOSFET is presented. The model uses the BSIM-BULK (formerly BSIM6) model at its core, which has been extended to include the overlap capacitance due to the drift region as well as quasi-saturation effect. The model is symmetric and continuous, is validated with the TCAD simulations and experimental 35- and 90V LDMOS and 40V VDMOS transistors, and shows excellent agreement.

FIG: Schematic of the LDMOS. Lightly doped n-region constitutes the drain. Majority of the applied drain voltage drops across this region, which protects the intrinsic transistor region from breakdown.

Manuscript received March 3, 2019; revised May 23, 2019 and July 24, 2019; accepted July 31, 2019. Date of publication August 26, 2019; date of current version September 20, 2019. This work was supported in part by the members of the Berkeley Center for Negative Capacitance Technology and the members of the Berkeley Device Modeling Center. The review of this article was arranged by Editor B. Iñiguez.

[paper] RESURF Model and Electrical Characteristics of Finger-Type STI Drain Extended MOS Transistors

RESURF Model and Electrical Characteristics of Finger-Type STI Drain Extended MOS Transistors
H. C. Tsai, R. H. Liou and C. Lien
IEEE Transactions on Electron Devices
vol. 63, no. 12, pp. 4603-4609, Dec. 2016

Abstract: Finger-type shallow trench isolation (finger STI) drain extended MOS transistors are fabricated and its electrical characteristics is studied. Polyplate on a finger STI served as a reduced surface field is adopted to enhance breakdown voltage (BV) by reducing the effective doping concentration of the drain extension (DE) finger. The conformal mapping method, which relates the reduction of the doping concentration to the width (z_o) of the DE finger, the gap (z_d) between the polyplate and the DE finger, and the STI depth (y_s), is used to estimate the reduction of the doping concentration theoretically. Based on this reduced doping concentration, a BV model is derived. The predictions of this model agree very well with the experimental data.

Keywords: Conformal mapping, Doping, Electric breakdown, MOS devices, Semiconductor process modeling, Silicon, Transistors, Drain extended MOS (DEMOS), Lateral double Diffused MOS (LDMOS), poly field plate, reduced surface field (RESURF)

doi: 10.1109/TED.2016.2605504
[read more...]

[Final Program] 11th International Workshop on Compact Modeling

11th International Workshop on Compact Modeling (IWCM 14)

January 23 (Thursday), 2014

Suntec Singapore Convention and Exhibition Centre (Room 309)

Workshop Program

9:00-9:10am Welcome address
Mansun Chan (workshop chair)

Session I: Modeling for Compact Semiconductor
Session Chair: Lining Zhang

9:10-9:35am Challenges and Prospects of Compact Modeling for Future Generation III-V/Si Co-integrated ULSI Circuit Design
Xing Zhou, Siau Ben Chiah, Binit Syamal, Hongtao Zhou, Arjun Ajaykumar, and Xu Liu; Nanyang Technological University, Singapore
9:35-10:00am A Large Signal Model for InP/InGaAs Double Heterojunction Bipolar Transistors
Yan Wang and Yuxia Shi; Tsinghua University, China
10:00-10:25am Analytical Modeling for AlGaN/GaN HEMTs
Aixi Zhang, Lining Zhang, Zhikai Tang, Xiaoxu Cheng*, Yan Wang*, Kevin J. Chen, and Mansun Chan; The Hong Kong University of Science and Technology, Hong Kong, China; *Tsinghua University, China

10:25-10:40am Break

Session II: Non-Classical Device Modeling and Platform
Session Chair: Xing Zhou

10:40-11:05am Developing i-MOS as a Compact Model Standardization Platform
Lining Zhang and Mansun Chan; The Hong Kong University of Science and Technology, Hong Kong, China
11:05-11:30am An Analytic Model for Nanowire Tunnel-FETs
Ying Liu, Jin He, Mansun Chan*, Caixia Du**, Yun Ye, Wei Zhao, Wen Wu and Wenping Wang; Peking University Shenzhen SOC Key Laboratory, China; *The Hong Kong University of Science and Technology, Hong Kong, China; **Shenzhen Huayue Teracale Chip Electronic Limited Co., China
11:30-11:55am A Channel Potential Based Model for SiO2- Core Si-Shell SRGMOSFET
Xiangyu Zhang, Jin He, Mansun Chan*, Caixia Du**, Yun Ye, Wei Zhao, Wen Wu and Wenping Wang; Peking University Shenzhen SOC Key Laboratory, China; *The Hong Kong University of Science and Technology, Hong Kong, China; **Shenzhen Huayue Teracale Chip Electronic Limited Co., China

11:55am-2:00pm Lunch

Session III: Power Device Modeling
Session Chair: Young June Park

2:00-2:25pm Compact Modeling of the Reverse Recovery Effect in LDMOS Body Diode (Invited)
M. Miyake; Hiroshima University, Japan
2:25-2:50pm Compact Modeling of the SiC IGBT Including the Switching at High Temperature
K. Matsuura, M. Miura-Mattausch, M. Miyake and H. J. Mattausch; Hiroshima University, Japan
2:50-3:15pm Experimental Verification of Power MOSFET Model under Switching Operations
A. Saito, M. Miura-Mattausch, M. Miyake, T. Umeda and H.J. Mattausch; Hiroshima University, Japan

3:15-3:30pm Break

Session IV: Reliability Modeling
Session Chair: Jin He

3:30-3:55pm 3D Monte Carlo Reaction-Diffusion Simulation Framework to model Time Dependent Dielectric Breakdown in BEOL Oxide
Seong Wook Choi and Young June Park; Seoul National University, Korea
3:55-4:20pm Development of NBTI and Channel Hot Carrier (CHC) Effect Models and their Application for Circuit Aging Simulation
Chenyue Ma, Hans Jürgen Mattausch, Kazuya Matsuzawa*, Seiichiro Yamaguchi*, Teruhiko Hoshida*, Masahiro Imade*, Risho Koh*, Takahiko Arakawa* and Mitiko Miura-Mattausch; Hiroshima University, Japan; * Semiconductor Technology Academic Research Center, Japan
4:20-4:45pm Modeling of the Surface Charges on Au Electrode Including Pseudocapacitance
Jooseong Kwon, Intae Jeong, Sungwook Choi and Young June Park; Seoul
National University, Korea

4:45-4:55pm Closing Remarks
Hans Juergen Mattausch (workshop co-chair)