Summer School on Organic Electronics and Neuromorphic Systems

Summer School on Organic Electronics and Neuromorphic Systems

June 17-20, 2024

will consist of a comprehensive set of classes aimed at doctoral or postdoctoral level researchers from both industry and academia. By means of a programme consisting of lectures, tutorials, advanced discussion groups, students will expand and refine their knowledge of organic materials, devices and circuits for microelectronics, as well as of neuromorphic devices and circuits with the world’s leading experts in these fields.

This Summer School is sponsored by the EU-funded BAYFLEX (Bayesian Inference with Flexible electronics for biomedical Applications) project. It is organized by the Department of Electronic, Electrical and Automatic Control Engineering (DEEEiA) of the Universitat Rovira i Virgili (URV), in Tarragona. The Chair of the Summer School is Prof. Benjamin Iñiguez.

PhD students can present posters showing some of their results in a session on June 20 afternoon. Interested PhD students can submit short abstracts of the results they want to present in the Poster Session.

Invited Speakers

• Jiri Pfleger, Czech Academy of Sciences (organic memristors),  
• Luisa Petti, University of Bolzano (organic electronics), 
• Chiara Bartollozzi, Italian Institute of Technology, Italy (event driven vision/robotics, CMOS) (neuromorphic), 
• Wilfred G. van der Wiel, Chair NanoElectronics Group | Director BRAINS Center for Brain-Inspired Nano Systems (organic +neuromorphic), 
• Sébastien Sanaur, IMT, France (neuromorphic), 
• François Danneville, IEMN, Lille, France (spiking neurons), 
• Simone Fabiano, University of Linköping, Sweden (organic + neuromorphic), 

Mini-Colloquium:

• Lluís F. Marsal, Universitat Rovira i Virgili, Tarragona, Spain, 
• Arokia Nathan, University of Cambridge, Darwin College, UK, 

• Paul Berger, Ohio State University, USA, 
• Radu A. Sporea, University of Surrey, UK, 
• Angèle Reynders, TU-Eindhoven, The Netherlands, 

[paper] artificial synapse

Md. Hasan Raza Ansari, Udaya Mohanan Kannan, and Nazek El-Atab

Silicon Nanowire Charge Trapping Memory for Energy-Efficient Neuromorphic Computing

IEEE Transactions on Nanotechnology (2023)

DOI 10.1109/TNANO.2023.3296673

SAMA Labs, CEMSE Division, KAUST, Thuwal 23955-6900, Saudi Arabia

Department of Electronic Engineering, Gachon University, Seongnam 13120, Korea

Abstract: This work highlights the utilization of the floating body effect and charge-trapping/de-trapping phenomenon of a Silicon-nanowire (Si-nanowire) charge-trapping memory for an artificial synapse of neuromorphic computing application. Charge trapping/de-trapping in the nitride layer characterizes the long-term potentiation (LTP)/depression (LTD). The accumulation of holes in the potential well achieves short-term potentiation (STP) and controls the transition from STP to LTP. Also, the transition from STP to LTP is analyzed through gate length scaling and high-κ material (Al2O3) for blocking oxide. Furthermore, the conductance values of the device are utilized for system-level simulation. System-level hardware parameters of a convolutional neural network (CNN) for inference applications are evaluated and compared to a static random-access memory (SRAM) device and charge-trapping memory. The results confirm that the Si-nanowire transistor with better gate controllability has a high retention time for LTP states, consumes low power, and archives better accuracy (91.27%). These results make the device suitable for low-power neuromorphic applications.

FIG: Schematic representation of biological and Si-nanowire charge trapping memory as an artificial synapse

Review of cryogenic neuromorphic hardware

Md Mazharul Islam¹, Shamiul Alam¹, Md Shafayat Hossain³, Kaushik Roy³, 

and Ahmedullah Aziz¹,

A review of cryogenic neuromorphic hardware

Journal of Applied Physics 133, no. 7 (2023): 070701

DOI: 10.1063/5.0133515

1Department of Electrical Engineering and Computer Science, University of Tennessee, Knoxville, Tennessee 37996, USA
2Department of Physics, Princeton University, Princeton, New Jersey 08544, USA
3Department of Electrical and Computer Engineering, Purdue University, West Lafayette, Indiana 47906, USA

ABSTRACT: The revolution in artificial intelligence (AI) brings up an enormous storage and data processing requirement. Large power consumption and hardware overhead have become the main challenges for building next-generation AI hardware. To mitigate this, neuromorphic computing has drawn immense attention due to its excellent capability for data processing with very low power consumption. While relentless research has been underway for years to minimize the power consumption in neuromorphic hardware, we are still a long way off from reaching the energy efficiency of the human brain. Furthermore, design complexity and process variation hinder the large-scale implementation of current neuromorphic platforms. Recently, the concept of implementing neuromorphic computing systems in cryogenic temperature has garnered intense interest thanks to their excellent speed and power metric. Several cryogenic devices can be engineered to work as neuromorphic primitives with ultra-low demand for power. Here, we comprehensively review the cryogenic neuromorphic hardware. We classify the existing cryogenic neuromorphic hardware into several hierarchical categories and sketch a comparative analysis based on key performance metrics. Our analysis concisely describes the operation of the associated circuit topology and outlines the advantages and challenges encountered by the state-of-the-art technology platforms. Finally, we provide insight to circumvent these challenges for the future progression of research.

FIG: (a) Biological neuron connected with multiple neurons through synapses. The inset shows the transportation of the neurotransmitter. (b) Electronic model of a neuromorphic system showing the integration of weighted spikes. (c) Several conventional hardware platforms. (d) Several cryogenic platforms for neuromorphic hardware. (e) Input spikes (Vin), corresponding membrane potential (Vmem), and output spike (Vout) of a leaky integrating and fire (LIF) neuron. An output spike is generated after Vmem crosses the threshold voltage (Vth). (f) Switching speed and switching energy comparison of conventional and cryogenic hardware.

2016 IEDM Tutorials

2016 International Electron Devices Meeting Tutorials

The tutorials are in their sixth year and are 90 minute stand-alone presentations on specialized topics taught by world-class experts. These tutorials provide a brief introduction to their respective fields, and facilitate understanding of the technical sessions. The tutorial sessions will take place on Saturday, Dec.3, 2016. Three tutorials are given in parallel in two time slots, at 2:45 p.m.and 4:30 p.m. respectively.

Topics presented at 2:45pm - 4:15pm:

• The Struggle to Keep Scaling BEOL, and What We Can Do Next
  Rod Augur, Distinguished Member of the Technical Staff, GlobalFoundries
• Physical Characterization of Advanced Devices
  Robert Wallace, Univ. Texas at Dallas
• Spinelectronics: From Basic Phenomena to Magnetoresistive Memory (MRAM) Applications
  Bernard Dieny, Chief Scientist, Spintec CEA

Topics presented at 4:30pm - 6:00pm:

• Electronic Circuits and Architectures for Neuromorphic Computing Platforms
  Giacomo Indiveri, Univ. of Zurich and ETH Zurich
• Present and Future of FEOL Reliability—from Dielectric Trap Properties to Reliable Circuit Operation
  Ben Kaczer, Principal Scientist, IMEC
• Embedded Systems and Innovative Technologies for IoT Applications
  Ali Keshavarzi, Vice President of R&D, Cypress Semiconductor

Register for the IEDM tutorials here: http://ieee-iedm.org/onsite-registration-center/online-registration/