Showing posts with label 180nm. Show all posts
Showing posts with label 180nm. Show all posts

Oct 24, 2016

Sub-Minimum-Area MPW Sharing

Is Your Multi-Project Wafer Project Smaller Than the Fab Minimum Area?

Share the minimum area with other MPW customers to save mask costs

With the cost of mask sets going up with every node, even a multi-project wafer (MPW) can break your NRE budget, particularly if you plan to run multiple test spins. At 28nm, a 6mm2 area tile can cost over $100,000.

One solution is to share the minimum tile area with someone else who is using the same technology and metal stack that you are targeting. We periodically get these kinds of requests from customers. Please contact directly star@esilicon.com if you would like eSilicon to list your own MPW shuttle sharing opportunity, or if you would like eSilicon to contact you when future MPW tile sharing opportunities are available.

Following are upcoming opportunities to share a multi-project wafer (MPW) tapeout with another eSilicon customer. If you are interested, just email eSilicon.

Multi-Project Wafer Minimum Tile Sharing Opportunities for TSMC Technologies
Tapeout
Month
Technology Metal Stack I/O Price/mm2 Minimum
Area
Final GDSII
Due
Tapeout
Date
Estimated
Ship Date
October 65nm MS RF GP  1P9M_6x1z1u  2.5V  $4,700 1mm2 October 10 October 12 November 23
65nm MS RF LP 1P9M_6x1z1u 2.5V  $4,700 1mm2 October 10 October 12 November 23
180nm MS RF G 1P6M_4x1u 3.3V $1,000 5mm2 October 24 October 26 December 7
November 40nm MS RF LP 1P10M 1.8V $7,500 1mm2 October 31 November 2 January 17