[paper] Fast and Expandable ANN-Based Extraction

Jeong, HyunJoon, SangMin Woo, JinYoung Choi, HyungMin Cho, Yohan Kim,

Jeong-Taek Kong, and SoYoung Kim

Fast and Expandable ANN-Based Compact Model and Parameter Extraction for Emerging Transistors IEEE Journal of the Electron Devices Society (2023)

DOI 10.1109/JEDS.2023.3246477

Abstract: In this paper, we present a fast and expandable artificial neural network (ANN)-based compact model and parameter extraction flow to replace the existing complicated compact model implementation and model parameter extraction (MPE) method. In addition to nanosheet FETs (NSFETs), our published ANN based compact modeling framework is easily extended to negative capacitance NSFETs (NC-NSFETs), which are attracting attention as next-generation devices. Each device is designed using a technology computer-aided design (TCAD) simulator. Using device structure parameters, temperature, and channel doping depth as input variables, we construct a dataset of electrical properties used for machine learning (ML)-based modeling. The accuracy of predicting device electrical characteristics with the proposed ANN-based compact model is less than a 1% error compared to TCAD, and simulation results of digital and analog circuits using the proposed compact model show less than a 3% error. This allows the ANN-based modeling framework to achieve accurate DC, AC, and transient simulations without restrictions on device technology. In particular, temperature and process variables such as channel doping depth, which are not defined in the compact model parameters, are easily added to the previously presented five key parameters. Instead of conventional complex compact modeling and MPE work, we propose a method to create fast, accurate, flexible, and expandable ML-based Verilog-A SPICE models with design technology co-optimization (DTCO) capabilities.

Fig A: Conventional model parameter extraction flow

Fig B: The proposed ANN-based model parameter extraction flow

Acknowledgments: We thank the reviewers for improving the contents of the paper. This work was supported by an Institute of Information & communications Technology Planning & Evaluation (IITP) grant funded by the Korean government (MSIT) (No.2021-0- 00754, Software Systems for AI Semiconductor Design) and by a National Research Foundation of Korea grant funded by the Korean government (MISP) (NRF-2020R1A2C1011831). The EDA tool was supported by the IC Design Education Center (IDEC), Korea

[paper] Radiation-Induced Fault Simulation of SOI/SOS CMOS LSI’s Using Universal Rad-SPICE MOSFET Model

Radiation-Induced Fault Simulation of SOI/SOS CMOS LSI’s 

Using Universal Rad-SPICE MOSFET Model

Konstantin O. Petrosyants, Lev M. Sambursky, Igor A. Kharitonov, Boris G. Lvov

J Electron Test (2017)

doi:10.1007/s10836-016-5635-8

Abstract: The methodology of modeling and simulation of environmentally induced faults in radiation hardened SOI/SOS CMOS IC’s is presented. It is realized at three levels: CMOS devices – typical analog or digital circuit fragments – complete IC’s. For this purpose, a universal compact SOI/SOS MOSFET model for SPICE simulation software with account for TID, dose rate and single event effects is developed. The model parameters extraction procedure is described in great depth taking into consideration radiation effects and peculiarities of novel radiation-hardened (RH) SOI/SOS MOS structures. Examples of radiation-induced fault simulation in analog and digital SOI/SOS CMOS LSI’s are presented for different types of radiation influence. The simulation results show the difference with experimental data not larger than 10–20% for all types of radiation.

The electrical schematics of SOS CMOS opamp and 4-bit counter are presented; two variants of either macromodel were used for body-tied partially-depleted transistors: a) core EKV-SOI/ BSIMSOI model; b) EKV-RAD/ BSIMSOI-RAD macromodel. [read more...]