The MOS-AK Modeling Working Group, a global compact/SPICE modeling and Verilog-A standardization forum, held its annual autumn workshop on September 12, 2016 in Lausanne (CH) as its 14th consecutive modeling event at the ESSDERC/ESSCIRC Conference. The event was coordinated by Larry Nagel, OEC (USA) and Andrei Vladimirescu, UCB (USA); ISEP (FR) representing the International MOS-AK Board of R&D Advisers. The workshop was co-sponsored by ASCENT Network (lead sponsor) and EPFL EDLab, with technical program sponsorship provided by the IEEE WiE Group (CH), Eurotraining and NEEDS of nanoHUB.org.
A group of the international academic researchers and modeling engineers attended 12 technical compact modeling presentations covering full development chain form the nanoscaled technologies thru semiconductor devices modeling to advanced IC design support. The MOS-AK speakers have shared their latest perspectives on compact/SPICE modeling and Verilog-A standardization in the dynamically evolving semiconductor industry and academic R&D.
The workshop was opened by Prof. J. Greer; Tyndall National Institute, the MOS-AK keynote speaker, who has introduced the ASCENT Network. The ASCENT is combined resources of Tyndall (Ireland), imec (Belgium) and Leti (France) nanofabrication capabilities and electrical characterization facilities integrated into a single research infrastructure present a truly unique R&D opportunity. It provides characterization community with access to advanced test chips, flexible fabrication and advanced test and characterization equipment to accelerate development of advanced models at scales of 14nm and below.
The event featured additional technical presentations covering compact model development, implementation, deployment and standardization. These contributions were delivered by leading academic and industrial experts, including: Denis Rideau; STM (F), presenting a modeling study of the drain current in advanced MOSFETs. Maria-Alexandra Paun; EPFL (CH), focusing on the humidity sensors based on MWCNTs/MMA composite in SOI CMOS technological process. Mike Brinson; London Met (UK), presenting QUCS-S - maturing GPL software package for circuit simulation and compact modeling of current and emerging technology devices. Alexander Kloes; THM Giessen (D), discussing a closed-form charge-based current model of organic TFT including non-linear injection effects. Jean-Michel Sallese; EPFL (CH), discussing an advances in analytical modeling. Marco Bellini, ABB CRC (CH), presenting extraction of compact models for EMI / EMC simulations of power devices. Muhammad Nawaz; ABB CRC (S), reviewed characterization and modeling of SiC MOSFET power modules. Mansun Chan; HKUST (HK), discussing concurrent device and circuit reliability simulation. Benjamin Iñiguez; URV (SP), talking about temperature dependent GIZO TFT modeling. Mike Schwarz; THM (D), discussing analytical III-V SB MOSFET modeling and its performance analysis from room to cryogenic temperature. Matthias Bucher; TUC (GR), giving an EKV3 model update. The presentations are available online for download at http://www.mos-ak.org/
The MOS-AK Modeling Working Group has various deliverables and initiatives including a book entitled "Open Source CAD Tools for Compact Modeling" and an open Verilog-A directory with models and supporting CAD software. The MOS-AK Association plans to continue its standardization efforts by organizing additional compact modeling meetings, workshops and courses in Europe, USA, India and China throughout 2016/2017 including:
* 9th International MOS-AK Workshop at Berkeley in the timeframe of IEDM and CMC meetings (Dec.7, 2016)
* Spring MOS-AK Workshop in Lausanne during DATE Conference (March 31 2017)
* 2nd Sino MOS-AK Workshop in Hangzhou (June 2017)
* 15th MOS-AK ESSDERC/ESSCIRC Workshop in Leuven (Sept.11, 2017)
About MOS-AK Association:
MOS-AK, an international compact modeling association primarily focused in Europe, to enable international compact modeling R&D exchange in the North/Latin Americas, EMEA and Asia/Pacific Regions. The MOS-AK Modeling Working Group plays a central role in developing a common language among foundries, CAD vendors, IC designers and model developers by contributing and promoting different elements of compact/SPICE modeling and its Verilog-A standardization and related CAD/EDA tools for the compact models development, validation/implementation and distribution.
About ASCENT Network:ASCENT provides fast and easy access to the world's most advanced CMOS technologies and infrastructure including access to 14nm CMOS device data, nanoscale test chips and device characterisation facilities at Tyndall (Ireland), imec (Belgium) and Leti (France). ASCENT has received funding from the European Union's Horizon 2020 research and innovation programme under grant agreement No 654384.
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