[paper] Scalable Open-Source Multi-Project SoC Architecture

Uriel Jaramillo-Toral, Susana Ortega-Cisneros, Héctor Emmanuel Muñoz-Zapata, 

Iraam Antonio López-Salas 

Silicluster v2: A Scalable Open-Source Multi-Project SoC Architecture 

in Sky130 CMOS Enabling High-Density Modular Integration

in IEEE Access, vol. 14, pp. 82876-82889, 2026

doi: 10.1109/ACCESS.2026.3698053. 

* CINVESTAV, Guadalajara, Jalisco, Mexico

* Tecnológico Nacional de México, ITA, Aguascalientes, Mexico

Abstract: The increasing availability of open-source electronic design automation (EDA) tools and publicly accessible process design kits (PDKs) has expanded access to integrated circuit (IC) development; however, scalable system-level integration frameworks capable of supporting heterogeneous digital, analog, and mixed-signal systems remain limited. This paper presents Silicluster Version 2 (Silicluster v2), a hierarchical and scalable multi-project system-on-chip (SoC) architecture implemented in 130 nm complementary metal-oxide-semiconductor (CMOS) technology using a fully open-source register-transfer-level (RTL) to Graphic Data System II (GDSII) layout design flow. The proposed architecture enables the structured integration of up to 256 independent digital, analog, and mixed-signal modules within a single chip while preserving modular isolation, reusability, and routing efficiency. In contrast to its previous digital-focused implementation, Silicluster v2 incorporates infrastructure supporting transistor-level analog layout, parasitic-aware mixed-domain co-simulation using Simulation Program with Integrated Circuit Emphasis (SPICE), and integration of synthesized standard-cell netlists alongside custom transistor-level blocks. A hierarchical multiplexed interconnection scheme and centralized clock-distribution strategy mitigate fanout, congestion, and timing-closure challenges inherent to high-density modular integration. The complete system is validated through design rule checking (DRC), layout-versus-schematic (LVS) verification, parasitic extraction, and static timing analysis (STA) at 10 MHz, targeting 1.8 V digital operation and 3.3 V analog operation. The results demonstrate the feasibility of constructing complex heterogeneous integrated circuits using exclusively open-source methodologies, establishing Silicluster v2 as a validated reference architecture for collaborative silicon integration and scalable multi-project chip development.

Fig: Graphical representation of the Silicluster v2 integration process within Caravel. The original user area is replaced by the Silicluster v2 wrapper, enabling high-density modular integration and resulting in a complete MPW-ready SoC while preserving the RISC-V subsystem and padframe infrastructure.

Acknowledgment: The authors gratefully recognize ChipFoundry for enabling the fabrication of Silicluster v2 through the MPW Program. Their support made the physical realization of the proposed architecture possible. They also acknowledge Toyohashi University of Technology (TUT) for its early-stage mentorship in analog design methodologies and the Centro de Investigación y de Estudios Avanzados del IPN, Unidad Guadalajara (CINVESTAV), for providing the academic environment and institutional framework that supported the development of this project.

26th Workshop Analog Circuits

26th Workshop Analog Circuits 

12.03.2026 and 13.03.2026

at Leibniz University Hannover

The workshop series offers a platform to present one's own ideas and discuss results with science and industry. The focus is on integrated analog and mixed-signal circuits.

The workshop will take place on 12.03.2026 and 13.03.2026 in the Royal Horse Stable of the University of Hannover.  Registration - Participation in the workshop is free of charge.

The programme will be compiled after the call for papers has been completed and is avalable online 

In the run-up to the 26th Workshop on Analog Circuits, the DE:Sign cooperation event on the topic of "Open Source Tools for Analog Design" will take place on the morning of 12.03.2026. In this event, the funded projects will present their current status on open design tools and methods for analogue design. Participants will receive an overview of the contribution of the respective projects to the development of technology open, accessible, and sustainable design chains in the sense of the DE:Sign guideline.

If you have any questions, please contact the organizers by e-mail at: analog2026@ims.uni-hannover.de

Verilog-AMS in Gnucap

Mixed-Signal Modelling and Simulation with Verilog-AMS

Verilog-AMS is a standardised modelling language widely used in analog and mixed-signal design, but without an open reference implementation. The language supports high-level behavioural descriptions as well as structural descriptions of systems and components. This Project will make substantial progress towards a Gnucap based free/libre Verilog-AMS implementation. Gnucap is a modular mixed-signal circuit simulator, and has been released under a copyleft license with the intent to avoid patent issues. Gnucap provides partial support for structural Verilog and encompasses an analog modelling language that has influenced the Verilog standards. We will enhance data structures and algorithms in Gnucap, and improve Verilog support on the simulator level. We will implement a Verilog-AMS behavioural model generator targetting Gnucap with the intent to support simulators with similar architecture later on. The project's own website:

http://gnucap.org/dokuwiki/doku.php/gnucap:projects:nlnet:verilogams

Task 1. modelgen-verilog: Provide a replacement for ADMS

Task 2. Verilog-AMS compliance on the simulator level

Task 3. Compiler optimisations

Acknowledgement: This project was funded through the NGI0 Entrust Fund, a fund established by NLnet with financial support from the European Commission's Next Generation Internet programme, under the aegis of DG Communications Networks, Content and Technology under grant agreement No 101069594.

VSD Free Webinar - Mixed-signal RISC-V based SoC on FPGA - 23rd July, 7pm IST

 

This 60-min webinar helps you get started with a basic mixed-signal FPGA flow, which can be extended to any complex SoC.VSD and RedwoodEDA conducts 5-day RISC-V based MYTH (Microprocessors for You in Thirty Hours) workshop using transaction level Verilog on Makerchip platform. For people who have done this workshop can use this webinar as an extension to the 5th Day, where RISC-V pipe-lined CPU coded in TL-Verilog is now converted to Verilog language and is a part of a mixed-signal SoC

If you are from ASIC/Physical design back-ground, this webinar will complement your existing work, and you would really get to know similarities and differences between ASIC and FPGA flow, which one is preferred under what conditions and why is it preferred

This single webinar connects VLSI students, analog designers, FPGA designers and ASIC designers. It is also an attempt to bring everyone on the same platform, and serves as a starting point for design verification

Stay tuned for follow-up series of FPGA webinars and 5-day hands-on high intensity FPGA workshop, which will be built around OpenFPGA framework and Makerchip visualization software, that enables the whole community to learn FPGA fundamentals along with labs, without actually having a physical FPGA board.

Agenda:

1. "FPGA on eSim"
   Guest Speaker - Prof. Kannan M Moudgalya, IIT Bombay
2. "chipIgnite Program"
   Guest Speaker - Mike Wishart, CEO eFabless
3. "Tapeout World Program"
   Guest Speaker - Naveed Sherwani, Chairman, OSFPGA
4. "Mixed-signal RISC-V based SoC on FPGA"
   Webinar Instructor - Shivani Shah

Webinar Curriculum:
1) Introduction
2) RVMYTH RISC-V Core
3) Why FPGAs ?
4) TL - Verilog to RTL verilog using Makerchip
5) Functional Simulation using iverilog
6) FPGA - Steps to create project
7) FPGA - Steps to generate IPs
8) FPGA - RTL simulation
9) FPGA - Synthesis
10) FPGA - Implementation and timing analysis
11) FPGA - Bit-stream generation, FPGA programming and ILA
12) Conclusion

Register here (if you don't see the form, please refresh page):
https://lnkd.in/gByg6fZ