Philippe Sauter∗, Thomas Benz∗, Paul Scheffler∗ , Frank K. Gurkaynak∗ , Luca Benini∗†
Insights from Basilisk:
Are Open-Source EDA Tools Ready for a Multi-Million-Gate, Linux-Booting RV64 SoC Design?
arXiv:2405.04257v2 [cs.AR] 8 May 2024
* Integrated Systems Laboratory, ETH Zurich, Switzerland
† Department of Electrical, Electronic, and Information Engineering, University of Bologna, Italy
Abstract: Designing complex, multi-million-gate application specific integrated circuits requires robust and mature electronic design automation (EDA) tools. We describe our efforts in enhancing the open-source Yosys+Openroad EDA flow to implement Basilisk, a fully open-source, Linux-booting RV64GC system-onchip (SoC) design. We analyze the quality-of-results impact of our enhancements to synthesis tools, interfaces between EDA tools, logic optimization scripts, and a newly open-sourced library of optimized arithmetic macro-operators. We also introduce a streamlined physical design flow with an improved power grid and cell placement integration. Our Basilisk SoC design was taped out in IHP’s open 130 nm technology. It achieves an operating frequency of 77 MHz (51 logic levels) under typical conditions, a 2.3 improvement compared to the baseline open-source EDA flow, while also reducing logic area by 1.6. Furthermore, tool runtime was reduced by 2.5, and peak RAM usage decreased by 2.9. Through collaboration with EDA tool developers and domain experts, Basilisk establishes solid "proof of existence" for a fully open-source EDA flow used in designing a competitive multi-million-gate digital SoC.
FIG: Layout files produced by running the original Iguana flow (a) and of Basilisk (b).
| Logic area (NAND2) | 1.1 MGE |
| Logic levelsa | 51 LL |
| Technology | 130 nm IHP |
| Operating frequency | 77 MHz |
| SRAM memory | 172 KiB (24 macros) |
| Chip / core area | 39 mm / 21 mm |
| IO count | 69 |
Acknowledgement: We thank Alan Mishchenko, Masahiro Fujita, Giovanni De Micheli, Andrea Costamagna, Alessandro Tempia Calvino, Osama Hammad Abdel Reheem, Matt Liberty, Martin Poviser, the Yosys team, Beat Muheim, and Zerun Jiang, for their valuable contributions to the research project. We further thank all contributors to the OS EDA tools.
We are deeply grateful to IHP for their generous support and providing us with the opportunity for an open-source tapeout of this scale.
This work was supported in part through the TRISTAN (101095947) project that received funding from the HORIZON KDT-JU programme
