Workshop on Advanced Integrated Circuit Design

U.S.-Japan Collaborative Workshop on Advanced Integrated Circuit Design

(Phase 2)

Fukuoka System LSI Development Center 2F

May 14 - May 15, 2024

https://www.kerc.or.jp/seminar/2024/04/5145152.html

In recent years, R&D and investment in semiconductors have become more active in countries around the world, and at the same time, the need for human resource development has been pointed out. In Japan in particular, the construction and attraction of factories for semiconductor "manufacturing" is accelerating, and various activities are being developed, but in the future, it is necessary to accelerate discussions on semiconductor "design". Against this backdrop, with the support of the U.S. Consulate in Fukuoka, we decided to hold a workshop in collaboration with the U.S. In December 2023, we held the U.S.-Japan Collaborative Workshop on Circuit Design (Phase 1), a state-of-the-art integrated circuit design, with the aim of learning about the latest situation in both countries through lectures on cutting-edge design technology and human resource development in Japan and the United States, as well as discussing the future direction and possibilities for international collaboration. We cover a wide range of topics, including open IC design, advanced analog and digital circuit design, generative AI processing (LLM) acceleration, optical circuit design, cryogenic classical and quantum computing, and new device technologies. Hybrid format (lectures can be held at Fukuoka venues and ZOOM Webinars), free of charge, with simultaneous English-Japanese interpretation. Therefore, it is a form that is easy to participate in. This is a good opportunity to learn about global trends, so not only those who specialize in semiconductors, but also those who are even a little interested in semiconductors, please join us. Students are also welcome to participate! In addition, we plan to have a simple hands-on session in the tutorial session, so if you are interested, please bring / prepare a laptop.

Outline of the event

Date & Time

DAY-1: May 14, 2024 10:00 a.m. ~ 4:00p.m.
DAY-2: May 15, 2024 10:00 a.m. ~ 4:05 p.m.

Hybrid format (lectures can be held at Fukuoka venues and ZOOM Webinars)
Online (Zoom Webinars)

Fukuoka Venue: Fukuoka System LSI Development Center 2F
(〒814-0001 3-8-33 Momochihama, Sawara-ku, Fukuoka City)
There is no parking lot at the venue, so if you come by car, please use the
nearby paid parking lot.

Participation Fee:  free

Application
[Application deadline: May 13]
Please apply from the link below (you can also apply for either Day-1 or Day-2 only). Simultaneous interpretation in English and → is available at the Fukuoka venue and ZOOM Webinars. The first 70 people to participate at the Fukuoka venue and the first 400 people to participate in the ZOOM Webinar will be closed to the first 400 people. If you wish to cancel after applying for the Fukuoka venue, please contact us as soon as possible. In addition, we are planning a simple hands-on, so please bring your laptop (you can participate without a laptop).

Application Form

Program Details  (subject to update) https://www.kerc.or.jp/seminar/2024/04/5145152.html

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Day-1: May 14, 10:00-16:00 (JST)

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10:00 - 10:05 Opening Remark and Overview of the Workshop, Mehdi Saligane/Koji Inoue, University of Michigan/Kyushu University

[Morning Session: Invited Talks]
10:05 - 10:10 Welcome Remarks from the U.S. Consulate in Fukuoka
10:10 - 10:55 LLMs on ASICs, Greg Kielian/Kauna Lei, Google Research
11:00 - 11:45 Teaching Mixed-Signal Design Using Open-Source Tools, Boris Murmann, University of Hawaii
11:45 - 13:00 Lunch Break

[Afternoon Session: Tutorials]
13:00 - 14:00 Photonic and Analog circuits with GDSFactory, Joaquin Matres/Troy Tamas, Google X/DoPlayDo, Inc.
14:00 - 14:15 Break
14:15 - 15:45 ReaLLMASIC: Build your own Lightweight LLM, Gregory Kielian/Kauna Lei/Shiwei Liu/Mehdi Saligane, Google Research/University of Michigan
15:45 - 16:00 Conclusion, Mehdi Saligane, University of Michigan

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Day-2: May 15th, 10:00-16:05 (JST) 

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10:00 - 10:05 Opening Remark and Overview of Day-2 Workshop, Mehdi Saligane/Koji Inoue, University of Michigan/Kyushu University
[Morning Session: Invited Talks]
10:05 - 10:50 Superconductor Computer Architecture: from Classical to Quantum, Ilkwon Byun, Kyushu University
10:50 - 11:35 Overview of new devices in the era of Beyond CMOS, Sadayuki Yoshitomi, Megachips
11:35 - 13:00 Lunch Break
[Afternoon Session: Tutorials]
13:00 - 13:55 (Tentative: GLayout), Anhang Li/Boris Murmann/Mehdi Saligane, University of Michigan/University of Hawaii
13:55 - 14:50 (Tentative: XLS: High-Level Synthesis), Johan Euphrosine, Google
14:50 - 15:05 Break
15:05 - 16:00 Pitfalls of Open-Source Chip Design Verification, Mitch Bailey, Efabless/ShuhariSystem
16:00 - 16:05 Conclusion and Overview of the phase-2 workshop activities, Mehdi Saligane/Koji Inoue, University of Michigan/Kyushu University

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Organizer

University of Michigan
Kyushu University System LSI Research Center Kyushu University
Quantum Computing Systems Research Center Kyushu University
Value Creation Semiconductor Human Resource Development Center

Co-organizers
Fukuoka Prefectural Foundation for the Promotion of Industry, Science and Technology Kyushu Economic Research Association

Sponsor
U.S. Consulate in Fukuoka

Inquiries
ic-design-ws 'at' slrc.kyushu-u.ac.jp (replace 'at' with @)
Okano, Business Development Department, TEL: 092-721-4907

[paper] integrated PD SOI CMOS microcantilever biosensor

Yi Liu, Yuan Tian, Cong Lin, Jiahao Miao & Xiaomei Yu*

A monolithically integrated microcantilever biosensor 

based on partially depleted SOI CMOS technology

Microsystems & Nanoengineering volume 9, Article number: 60 (2023)

DOI: 10.1038/s41378-023-00534-y

* School of Integrated Circuits, Peking University, National Key Laboratory of Science and Technology on Micro/Nano Fabrication, Beijing, 100871, China

Abstract: This paper presents a monolithically integrated aptasensor composed of a piezoresistive microcantilever array and an on-chip signal processing circuit. Twelve microcantilevers, each of them embedded with a piezoresistor, form three sensors in a Wheatstone bridge configuration. The on-chip signal processing circuit consists of a multiplexer, a chopper instrumentation amplifier, a low-pass filter, a sigma-delta analog-to-digital converter, and a serial peripheral interface. Both the microcantilever array and the on-chip signal processing circuit were fabricated on the single-crystalline silicon device layer of a silicon-on-insulator (SOI) wafer with partially depleted (PD) CMOS technology followed by three micromachining processes. The integrated microcantilever sensor makes full use of the high gauge factor of single-crystalline silicon to achieve low parasitic, latch-up, and leakage current in the PD-SOI CMOS. A measured deflection sensitivity of 0.98 × 10−6 nm−1 and an output voltage fluctuation of less than 1 μV were obtained for the integrated microcantilever. A maximum gain of 134.97 and an input offset current of only 0.623 nA were acquired for the on-chip signal processing circuit. By functionalizing the measurement microcantilevers with a biotin-avidin system method, human IgG, abrin, and staphylococcus enterotoxin B (SEB) were detected at a limit of detection (LOD) of 48 pg/mL. Moreover, multichannel detection of the three integrated microcantilever aptasensors was also verified by detecting SEB. All these experimental results indicate that the design and process of monolithically integrated microcantilevers can meet the requirements of high-sensitivity detection of biomolecules.

FIG: a) Micrograph of the fabricated integrated microcantilever sensor IC.
b) SEM photograph of the microcantilever array

Acknowledgements: This research was funded by the National Natural Science Foundation of China (Grant No. 61935001).

Open Access: this article is licensed under a Creative Commons Attribution 4.0 International License 

[paper] Cantilever with Carbon Piezoresistor

Jongmoon Jang, Giulia Panusa, Giovanni Boero and Juergen Brugger 

SU-8 Cantilever with Integrated Pyrolyzed Glass-Like Carbon Piezoresistor

Microsyst Nanoeng 8, 22 (2022)

DOI:10.1038/s41378-022-00351-9

Abstract: Glass-like carbon (GC) is a nongraphitizing material composed entirely of carbon atoms produced from selected organic polymer resins by controlled pyrolysis in an inert atmosphere. The GC properties are a combination of the properties of glass, ceramic, and graphite, including hardness, low density, low thermal conductivity, high chemical inertness, biocompatibility, high electrical conductivity, and microfabrication process compatibility. Despite these unique properties, the application of GC in mechanical sensors has not been explored thus far. Here, we investigate the electrical, structural, and chemical properties of GC thin films derived from epoxy-based negative photoresist SU-8 pyrolyzed from 700 to 900°C. In addition, we fabricated microGC piezoresistors pyrolyzed at 700 and 900 °C and integrated them into nonpyrolyzed SU-8 cantilevers to create microelectromechanical systems (MEMS) mechanical sensors. The sensitivities of the GC sensor to strain, force, surface stress, and acceleration are characterized to demonstrate their potential and limits for electromechanical microdevices.

Fig: Design and layout of the glass-like carbon (GC)-based sensor:

a.) Schematic drawing of the GC strain sensor, and

b.) Enlarged optical microscopic image of a fabricated GC piezoresistor

Acknowledgements: The authors thank the Center of Micro/Nanotechnology (CMi) of EPFL for the microelectromechanical system (MEMS) fabrication support and Bio-Micro Robotics laboratory with Professor Hongsoo Choi of DGIST for the microforce probe system facility support. This work received funding from the European Research Council (ERC) under the European Union’s Horizon 2020 research and innovation program (Project “MEMS 4.0”, ERC-2016-ADG, Grant Agreement No. 742683) and the National Research Foundation of Korea (NRF) grant funded by the Korean government (MSIT) (No. 2020R1F1A107422211).

[paper] 3D integrated GaN/RF-SOI SPST switch

Frédéric Drillet, Jérôme Loraine, Hassan Saleh, Imene Lahbib, Brice Grandchamp, Lucas Iogna-Prat, Insaf Lahbib, Ousmane Sow, Albert Kumar and Gregory U'Ren 

RF Small and large signal characterization of a 3D integrated GaN/RF-SOI SPST switch 

International Journal of Microwave and Wireless Technologies, pp. 1–6, 2021.

*X-FAB France, Corbeil-Essonnes (F)

Abstract: This paper presents the radio frequency (RF) measurements of an SPST switch realized in gallium nitride (GaN)/RF-SOI technology compared to its GaN/silicon (Si) equivalent. The samples are built with an innovative 3D heterogeneous integration technique. The RF switch transistors are GaN-based and the substrate is RF-SOI. The insertion loss obtained is below 0.4 dB up to 30 GHz while being 1 dB lower than its GaN/Si equivalent. This difference comes from the vertical capacitive coupling reduction of the transistor to the substrate. This reduction is estimated to 59% based on a RC network model fitted to S-parameters measurements. In large signal, the linearity study of the substrate through coplanar waveguide transmission line characterization shows the reduction of the average power level of H2 and H3 of 30 dB up to 38 dBm of input power. The large signal characterization of the SPST shows no compression up to 38 dBm and the H2 and H3 rejection levels at 38 dBm are respectively, 68 and 75 dBc.

Fig: X-FAB 3D integration proposal cross-section (left) and the picture of a GaN coupon (right).

Acknowledgement: We would like to acknowledge the Nano2022 program for partially funding this work.

Supplementary material: The supplementary material for this article can be found at DOI: 0.101/1759078721000076