[paper] ULTRARAM Neuromorphic Memory Device

Abhishek Kumar, Peter D. Hodgson, Manus Hayne, and Avirup Dasgupta

Artificial synapse based on ULTRARAM memory device for neuromorphic applications

Journal of Applied Physics 139, no. 12 (2026)

DOI: 10.1063/5.0314826

1. Department of Electrical Engineering and Computer Sciences, UCB (USA)

2. Department of Physics, Lancaster University, Lancaster LA1 4YB (UK)

3. Quinas Technology Limited, Lancaster LA1 4YB, (UK)

4. Department of Electronics and Communication Engineering, IIT Roorkee (IN)

Abstract: The memory demands of large-scale deep neural networks (DNNs) require synaptic weight values to be stored and updated in off-chip memory, such as dynamic random-access memory, which reduces energy efficiency and increases training time. Monolithic crossbar or pseudo-crossbar arrays using analog non-volatile memories, which can store and update weights on-chip, present an opportunity to efficiently accelerate DNN training. In this article, we present on-chip training and inference of a neural network using an ULTRARAM memory device-based synaptic array and complementary metal–oxide–semiconductor (CMOS) peripheral circuits. ULTRARAM is a promising emerging memory exhibiting high endurance (⁠> 10E7P/E cycles), ultrahigh retention (⁠>1000 years), and ultralow switching energy per unit area. A physics-based compact model of ULTRARAM memory device has been proposed to capture the real-time trapping/de-trapping of charges in the floating gate and utilized for the synapse simulations. A circuit-level macro-model is employed to evaluate and benchmark the on-chip learning performance in terms of area, latency, energy, and accuracy of an ULTRARAM synaptic core. In comparison with CMOS-based design, it demonstrates an overall improvement in area and energy by 1.8x and 1.52x⁠, respectively, with 91% of training accuracy.

FIG: Schematic of an ULTRARAM memory cell and the corresponding transmission electron microscope image of the device’s epilayers

Acknowledgments: This work was supported in part by the Quinas Technology Limited, Lancaster, United Kingdom; Indian Institute of Technology Roorkee, India; and Prime Minister’s Research Fellowship, Ministry of Education, Government of India under Grant No. PM-31-22-773-414.

Data Availability: The data that support the findings of this study are available within the article.