Showing posts with label junctionless FET. Show all posts
Showing posts with label junctionless FET. Show all posts

Jan 21, 2025

[paper] Nanowire Biosensor Analytical Model

Ashkhen Yesayan, Aleksandr Grabski, Farzan Jazaeri, Jean-Michel Sallese
Design-Oriented Analytical Model for Nanowire Biosensors Including Dynamic Aspects
IEEE TED (2025) DOI 10.1109/TED.2025.3526113

Abstract: Nanowire Field Effect Transistor (NWFET) biosensors are known to be highly sensitivity devices that can detect extremely low concentrations of biomolecules. In this paper, we present an analytical model alongside with numerical simulations to calculate the sensitivity of NWFET biosensors. The model accounts for biosensing dynamics as well as diffusion of ions in the solution and across the functionalized layer. The signal-to-noise ratio is also estimated, which gives a lower limit in terms of sensitivity. The model is physics based and is validated against a commercial multiphysics simulations and experimental data. It predicts the bio-sensitivity down to femtomolar concentration of biomolecules without any fitting parameter.

FIG: Schematic structure of device (a), the charge distribution in theoretical model (b) 
and Si NWFET sensitivity simulated with presented model (c)

Acknowledgement: This work was supported by the Science Committee of RA, in the frames of the research project No:21T-2B321.



Oct 7, 2020

[paper] Parameter Extraction in JFETs

Nikolaos Makris1, Matthias Bucher1, Member, IEEE, Loukas Chevas1, Farzan Jazaeri2
and Jean-Michel Sallese2
Free Carrier Mobility, Series Resistance, and Threshold Voltage Extraction
in Junction FETs
in IEEE Transactions on Electron Devices, 
Special Section on ESSDERC/ESSCIRC 2020
DOI: 10.1109/TED.2020.3025841.

1School of Electrical and Computer Engineering, TU Crete (GR)
2Ecole Polytechnique Fédérale de Lausanne, EPFL (CH)

Abstract: In this brief, extraction methods are proposed for determining the essential parameters of double gate junction field-effect transistors (FETs). First, a novel method for determining free carrier effective mobility, similar to a recently proposed method for MOSFETs, is developed. The same method is then extended to cover also the case when series resistance is present, while series resistance itself may be determined from the measurement from two FETs with different channel lengths. The key technological and design parameter is the threshold voltage, which may be unambiguously determined from the transconductance-to-current ratio with a constant-current method. The new methods are shown to be effective over a wide range of technical parameters, using technology computer-aided design simulations.

Fig: Extraction of carrier mobility for DG JFETs in linear region at 300K 
a) corresponding output conductance gds and constituents ∂gds/∂Vds and 2Qsc,d/b, and 
b) extracted mobility for long- and moderate-length devices close agreement with the constant, nonfield-dependent mobility (μ = 826 cm2/Vs) used in the TCAD simulations.

Aknowlegement: This work was supported in part by the INNOVATION-EL-Crete Project under Grant MIS 5002772.