[paper] Compact model of 3D NAND

Kul Lee and Hyungcheol Shin

Distinguishing capture cross section parameter between 

in GIDL erase compact model and TCAD

Japanese Journal of Applied Physics. 2021 Oct 14.

 
ISRC and School of Electrical Engineering and Computer Science, Seoul National University, (KR)
 

Abstract: Compact model of 3D NAND enables simulation at circuit- or system- level. Although compact model for gate-induced-drain-leakage(GIDL)-assisted erase has been proposed in previous study, it is difficult to be used practically because it has not been properly validated. In particular, capture-cross-section (CCS) value that is far from the real value is used. Also, it doesn’t consider the latest device structure and its operation. In this paper, conventional GIDL-assisted erase compact model is validated using TCAD and improved more practically. It is confirmed that CCS should be distinguished in TCAD and compact model due to their different definition in each of them. Based on their physical differences, equation that can interconvert them is proposed and the model is successfully validated with proper CCS. Finally, the advanced GIDL-assisted erase compact model considering tapered angle, single-side injection and word-line voltage is suggested.

Fig: Schematic cross section of 3D NAND string considering tapered angle. Double stacking and singe-side GIDL injection are assumed. It is assumed that the upper and lower stacks have the same dimension parameters.