[paper] Compact Model of Graphene FETs

Nikolaos Mavredakis, Anibal Pacheco-Sanchez, Oihana Txoperena,

Elias Torres, and David Jiménez

A Scalable Compact Model for the Static Drain Current of Graphene FETs

IEEE TED, Vol. 71, No. 1, January 2024

DOI:  10.1109/TED.2023.3330713

1 Departament d’Enginyeria Electrònica, Escola d’Enginyeria, UAB, 08193 Bellaterra, Spain
2 Graphenea Semiconductor SLU, 20009 San Sebastián, Spain.

Abstract: The main target of this article is to propose for the first time a physics-based continuous and symmetric compact model that accurately captures I–V experimental dependencies induced by geometrical scaling effects for graphene field-effect transistor (GFET) technologies. Such a scalable model is an indispensable ingredient for the boost of large-scale GFET applications, as it has been already proved in solid industry-based CMOS technologies. Dependencies of the physical model parameters on channel dimensions are thoroughly investigated, and semi-empirical expressions are derived, which precisely characterize such behaviors for an industry-based GFET technology, as well as for others developed in the research laboratory. This work aims at the establishment of the first industry standard GFET compact model that can be integrated in circuit simulation tools and, hence, can contribute to the update of GFET technology from the research level to massive industry production.

Fig: Graphenea GFET schematic cross-section not drawn to scale. Graphene under metal contacts is not shown.The drain current has explicit derivation in respect to Qgr, where Qt and Qp(n) are the transport sheet and p(n)-type charges, respectively; Vc is the chemical potential, h is the reduced Planck constant, uf is the Fermi velocity, e is the electron charge, and k is a coefficient. Qt and, thus, ID can be calculated according to Vc polarity at source (Vcs) and drain (Vcd), respectively. Hence, at n-type region where Vcs, Vcd > 0 and Qp = 0

Acknowledgements: This work was supported in part by the European Union’s Horizon 2020 Research and Innovation Program GrapheneCore3 under Grant 881603; in part by the Ministerio de Ciencia, Innovación y Universidades under Grant RTI2018-097876-B-C21 (MCIU/AEI/ FEDER, UE), Grant FJC2020-046213-I, and Grant PID2021-127840NBI00 (MCIN/AEI/FEDER, UE); in part by the European Union Regional Development Fund within the Framework of the ERDF Operational Program of Catalonia 2014–2020 with the Support of the Department de Recerca i Universitat, with a grant of 50% of Total Cost Eligible; and in part by the GraphCAT Project under Grant 001-P-001702. 

[paper] An Accurate Analytical Modeling of Contact Resistances in MOSFETs

G. Bokitko, D. S. Malich, V. O. Turin*, and G. I. Zebrev

An Accurate Analytical Modeling of Contact Resistances in MOSFETs

Preprint · May 7, 2021 DOI: 10.13140/RG.2.2.29348.40321

National Research Nuclear University MEPHI, Moscow, Russia;
*Orel State University, Russia;

Abstract: As the MOSFET channel lengths decrease, the influence of parasitic source-drain resistance on the current characteristics becomes more and more important. The contact resistance is becoming a growing impediment to transistor power and performance scaling. This is a common challenge for SOI FETs, FinFETs and GAAFETs and any other type of transistor. Most of the modern compact models that are used in circuits simulations are too much technology oriented. We find it important to construct an analytical approach that could be served as a basis for compact modeling. This approach is based on analytical solution Kirchhoff’s equations and on the diffusion-drift field effect transistor model.

Fig: Equivalent MOSFET circuit with series resistance

[paper] Analysis of 2D Transistors

Guoli Li, Zizheng Fan, Nicolas André, Member, IEEE, Yongye Xu, Ying Xia, Benjamín Iñíguez, Fellow, IEEE, Lei Liao, Senior Member, IEEE, and Denis Flandre, Senior Member, IEEE

Non-Linear Output-Conductance Function for Robust Analysis of Two-Dimensional Transistors

IEEE Electron Device Letters, 42(1), pp.94-97

DOI: 10.1109/LED.2020.3042212

Abstract: In this work, we explore the outputconductance function (G-function) to interpret the device characteristics of two-dimensional (2D) semiconductor transistors. Based on analysis of the device output conductance, the carrier mobility, and the channel as well as contact resistance are extracted. Thereafter the currentvoltage (IV) characteristics of black phosphorous (BP) and MoS2 transistors from room to low temperature are modeled and compared to experiments. The G-function model proves its reliability and accuracy in parameter extraction and IV modeling of 2D transistors, regardless of the n- or p- type, the short- or long-channel and the Schottky or Ohmic contact. Moreover, this works shows its high potential in the device modeling and further circuit design of the 2D transistors, requiring only few parameters and simulating precise IV characteristics.

G-Function Model (for Linear and Non-Linear Cases), the Rch and Rc can be calculated for both the Ohmic and Schottky contacts in the 2D transistors: 

Aknowlegement: This work was supported in part by the National Key Research and Development Program of China under Grant 2018YFA0703700; in part by the National Natural Science Foundation of China under Grant 61925403, Grant 61851403, and Grant 62004065; in part by the Hunan Natural Science Foundation under Grant 2020JJ5087; and in part by the Technology Program (Major Project) of Changsha under Grant kq1902042.

[paper] Organic semiconductor (OSC) OFETs

Boyu Peng, Ke Cao* Albert Ho Yuen Lau, Ming Chen, Yang Lu* and Paddy K. L. Chan

Crystallized Monolayer Semiconductor for Ohmic Contact Resistance, High Intrinsic Gain, and High Current Density

Adv. Mater. 2020, 32, 2002281 

DOI:10.1002/adma.202002281

Department of Mechanical Engineering, The University of Hong Kong, Pokfulam Road (HK)

*Department of Mechanical Engineering, City University of Hong Kong, Kowloon (HK)

Abstract: The contact resistance limits the downscaling and operating range of organic field-effect transistors (OFETs). Access resistance through multilayers of molecules and the nonideal metal/semiconductor interface are two major bottlenecks preventing the lowering of the contact resistance. In this work, monolayer (1L) organic crystals and nondestructive electrodes are utilized to overcome the abovementioned challenges. High intrinsic mobility of 12.5 cm2 V−1 s−1 and Ohmic contact resistance of 40 Ω cm are achieved. Unlike the thermionic emission in common Schottky contacts, the carriers are pre- dominantly injected by field emission. The 1L-OFETs can operate linearly from VDS = −1 V to VDS as small as −0.1 mV. Thanks to the good pinch-off behavior brought by the monolayer semiconductor, the 1L-OFETs show high intrinsic gain at the saturation regime. At a high bias load, a maximum current density of 4.2 µA µm−1 is achieved by the only molecular layer as the active channel, with a current saturation effect being observed. In addition to the low contact resistance and high-resolution lithography, it is suggested that the thermal management of high-mobility OFETs will be the next major challenge in achieving high-speed densely integrated flexible electronics.

Fig: a) Schematic charge accumulation and b) output curves of short-channel OFETs. c) Schematic charge accumulation and d) output curves of source-gated transistors. e) Schematic charge accumulation and f) output curves of 1L-OFETs. 

Acknowledgements: The authors gratefully acknowledge the support from the General Research Fund (GRF) under Grant Nos. HKU 17264016 and HKU 17204517, University of Hong Kong Seed Funding Grant Nos. 201711159068 and 201611159208. The authors appreciate Prof. Xin Cheng and Xin Zhuang from Southern University of Science and Technology for their support on e-beam lithography. The authors also thank Dr. Hagen Klauk and James W. Borchert for the fruitful discussions and suggestions.