The 22nd IEEE International Symposium on Power Semiconductor Devices and ICs will take place in Hiroshima (Japan) on June 6-10 2010. The deadline for abstract submission is October 30 2009 .ISPSD is the main international conference on the areas of power semiconductor devices, power integrated circuits, their hybrid technologies, and applications.Topics include: processes, materials, CAD/Simulation, devices, power ICs, packaging and applications.For researchers interested in compact modeling of power semiconductor devices, ISPSD is a top event to present and get to know the last results in this field. "Device & circuit simulation" is explicitly mentioned as one of the subtopic in the "CAD/Simulation" topic. Compact modeling fits very well this subject. And of course, there is a subtopic of "Modeling" in the "Device" topic.
I imagine that the developers of the well known HiSIM models, who work in the Hiroshima University, will be around, so this conference can be a bussiness oportunity for compact model developers and users, including circuit designers.
Aug 17, 2009
Aug 15, 2009
ISCAS'10
The 2010 IEEE International Symposium of Circuits and Systems (ISCAS 2010) will be held in Paris (France), on May 30-June 3 2010. It will take place at the Convention Center at Disney’s Hotel New York, in Paris. It will be supported by the Institut Supérieur d’Electronique de Paris.
ISCAS is the largest conference in the area of Circuits and Systems. It is sponsored by the IEEE Circuits and Systems Society. Prestigeous speakers in this field are always invited. ISCAS 2010 will focus on on circuits and systems employing nanodevices (both extremely scaled CMOS and non-CMOS devices) and circuit fabrics (mixture of standard CMOS and evolving nano-structure elements) and their implementation cost, switching speed, energy efficiency, and reliability.
The scope of ISCAS 2010 includes all topics related to integrated circuits and systems. Papers on compact modeling for circuit design are considered to address some of the topic of the call. In fact, every year a number of interesting papers on compact modeling are presented at ISCAS.
The deadline for paper submission is October 9 2010.
It is important to mention that in ISCAS posters are very well considered, as important as oral presentations. Many authors choose poster as their presentation format. Besides, a student paper contest will be held at ISCAS 2010 and sponsored by the Circuits and Systems Society.
On the other hand, a "a very entertaining social program is planned. Special tours to tourist attractions will be available to the Symposium attendees and their guests." It Sounds promising, anyway.
ISCAS is the largest conference in the area of Circuits and Systems. It is sponsored by the IEEE Circuits and Systems Society. Prestigeous speakers in this field are always invited. ISCAS 2010 will focus on on circuits and systems employing nanodevices (both extremely scaled CMOS and non-CMOS devices) and circuit fabrics (mixture of standard CMOS and evolving nano-structure elements) and their implementation cost, switching speed, energy efficiency, and reliability.
The scope of ISCAS 2010 includes all topics related to integrated circuits and systems. Papers on compact modeling for circuit design are considered to address some of the topic of the call. In fact, every year a number of interesting papers on compact modeling are presented at ISCAS.
The deadline for paper submission is October 9 2010.
It is important to mention that in ISCAS posters are very well considered, as important as oral presentations. Many authors choose poster as their presentation format. Besides, a student paper contest will be held at ISCAS 2010 and sponsored by the Circuits and Systems Society.
On the other hand, a "a very entertaining social program is planned. Special tours to tourist attractions will be available to the Symposium attendees and their guests." It Sounds promising, anyway.
ICMTS 2010
The IEEE 2010 ICMTS (International Conference Microelectronic Test Structures) has launched the final call for papers (deadline: Sept. 18, 2009). Authors are asked to submit a two or three page extended abstract in PDF file format (font-embedded) including a 500- to 1500-word summary, major figures, and data for review. ICMTS'10 will be held between March 22 – 25, 2010, in Hiroshima (Japan), and there is a suggested topic including "Device and Circuit Modeling, Parameter Extraction RF device modeling".
I imagine that the developers of the well known HiSIM models, who work in the Hiroshima University, will be around, so this conference can be a bussiness oportunity for compact model developers and users, including circuit designers.
The conference will be preceded by a one-day Tutorial Short Course on Microelectronic Test Structures on March 22, 2010. There will be an equipment exhibition relating to test structure measurements. A Best Paper award will be presented by the Technical Program Committee.
ICMTS has always an excellent social programme. There is always a very interesting excursion tour, and a wonderful gala dinner. And the Hiroshima cuisine is delicious...
I imagine that the developers of the well known HiSIM models, who work in the Hiroshima University, will be around, so this conference can be a bussiness oportunity for compact model developers and users, including circuit designers.
The conference will be preceded by a one-day Tutorial Short Course on Microelectronic Test Structures on March 22, 2010. There will be an equipment exhibition relating to test structure measurements. A Best Paper award will be presented by the Technical Program Committee.
ICMTS has always an excellent social programme. There is always a very interesting excursion tour, and a wonderful gala dinner. And the Hiroshima cuisine is delicious...
Aug 14, 2009
Compact Modeling Job Vacancy at TU Ilmenau, Germany
The RF & Nano Device group at TU Ilmenau is seeking a candidate for a position in the frame of a European Marie Curie Project.
The candidate will work on compact modeling of high-frequency transistors, in particular HEMTs (High Electron Mobility Transistor). During several months he or she will also work at a semiconductor foundry in the UK in the frame of a secondment agreement between the foundry and TU Ilmenau.
Contract details: Temporary contract to carry out a Ph D, starting date January 2010.
Application deadline: 31 October 2009.
Contact: PD Dr. Frank Schwierz, email: frank.schwierz@tu-ilmenau.de
Requirements: Candidates should be a Ph.D. student having already earned a Master or Dipl.-Ing. degree in electrical engineering, preferably in semiconductor electronics. Good skills in written and spoken English are mandatory.
Desirable is experience in the areas of semiconductor device physics and device modeling and simulation.
The candidate will work on compact modeling of high-frequency transistors, in particular HEMTs (High Electron Mobility Transistor). During several months he or she will also work at a semiconductor foundry in the UK in the frame of a secondment agreement between the foundry and TU Ilmenau.
Contract details: Temporary contract to carry out a Ph D, starting date January 2010.
Application deadline: 31 October 2009.
Contact: PD Dr. Frank Schwierz, email: frank.schwierz@tu-ilmenau.de
Requirements: Candidates should be a Ph.D. student having already earned a Master or Dipl.-Ing. degree in electrical engineering, preferably in semiconductor electronics. Good skills in written and spoken English are mandatory.
Desirable is experience in the areas of semiconductor device physics and device modeling and simulation.
Second International Workshop on Compact Thin-Film Transistor (TFT) Modeling for Circuit Simulation: Deadline extended
The Second International Workshop on Compact Thin-Film Transistor (TFT) Modeling for Circuit Simulation will be held at the University College London (UCL) in London (UK) on September 25 2009.
This workshop is intended to provide a forum for discussions and current practices on compact TFT modeling. The workshop is sponsored by IEEE EDS Compact Modeling Technical Committee in collaboration with IEEE UCL-Cambridge University EDS/LEOS Chapter joint chapter that is in the process of formation. Topics include include:
• Physics of TFTs and operating principles
• Compact TFT device models for circuit simulation
• Model implementation and circuit analysis techniques
• Model parameter extraction techniques
• Applications of compact TFT models in emerging products
• Compact models for interconnects in active matrix flat panels
Prospective authors should submit a 500-word abstract to: m.bauza@ucl.ac.uk
THE ABSTRACT SUBMISSION DEADLINE IS AUGUST 18 2009.
HOWEVER, ABSTRACTS WILL BE CONSIDER EVEN AFTER THE OFFICIAL SUBMISSION DEADLINE.
If their abstract is accepted, the authors will be invited to submit of a 4-page paper to be included in proceedings. The deadline is September 14, 2009.
This is the only workshop especifically devoted to the compact modeling of TFT!
This workshop is intended to provide a forum for discussions and current practices on compact TFT modeling. The workshop is sponsored by IEEE EDS Compact Modeling Technical Committee in collaboration with IEEE UCL-Cambridge University EDS/LEOS Chapter joint chapter that is in the process of formation. Topics include include:
• Physics of TFTs and operating principles
• Compact TFT device models for circuit simulation
• Model implementation and circuit analysis techniques
• Model parameter extraction techniques
• Applications of compact TFT models in emerging products
• Compact models for interconnects in active matrix flat panels
Prospective authors should submit a 500-word abstract to: m.bauza@ucl.ac.uk
THE ABSTRACT SUBMISSION DEADLINE IS AUGUST 18 2009.
HOWEVER, ABSTRACTS WILL BE CONSIDER EVEN AFTER THE OFFICIAL SUBMISSION DEADLINE.
If their abstract is accepted, the authors will be invited to submit of a 4-page paper to be included in proceedings. The deadline is September 14, 2009.
This is the only workshop especifically devoted to the compact modeling of TFT!
Aug 10, 2009
Aug 4, 2009
Q2 semiconductor sales up 17%, industry is 'returning to normal seasonal growth patterns,' SIA reports
I copy here an article originally published in EDN:(I mean, finally good news!)
Focused supply chain management by both producers and customers helped to moderate the impact of the global economic recession on the industry, SIA reports.
“The fourth-consecutive monthly increase in sales is one indicator the industry is returning to normal seasonal growth patterns,” said SIA President George Scalise in a statement.
Focused supply chain management by both producers and customers helped to moderate the impact of the global economic recession on the industry, SIA reports.
By Suzanne Deffree, Managing Editor, News -- Electronic News, 8/3/2009
Although sales numbers were a mixed bag of results, the SIA (Semiconductor Industry Association) this morning reported on Q2, June, and first half revenue with palatable optimism for a semiconductor industry recovery.
Q2 recorded a sequential worldwide sales increase of 17% and a 20% year-over-year decline for the quarter. Q2 sales of $51.7 billion were capped off by month of June sales at $17.2 billion, an increase of 3.7% from May when sales were $16.6 billion, but 20% lower than the $21.6 billion reported for June 2008.
While June continued a month-over-month sales growth trend that began in March when sales inched up 3.3% on February's numbers, total 2009 first half sales of $95.9 billion were still 25% below the first six months of 2008, when sales were $127.5 billion, SIA data showed.
|
Scalise said focused supply chain management by both producers and customers helped to moderate the impact of the global economic recession on the industry. “Inventories have been closely managed, encouraging us to believe that the sequential increase in quarterly sales represents a gradual recovery of demand,” he said.
Scalise and the SIA aren't the only optimistic parties in the semiconductor industry. Several industry analysts and market research companies including Gartner and iSuppli have recently become more positive in their forecasts for key demand drivers.
“Consensus estimates for unit sales of PCs are now in the range of minus 5% to flat compared to 2008, whereas earlier forecasts were projecting year-on-year unit declines of 9 to 12%," Scalise noted. "In cell phone handsets, analysts now believe the unit decline will be in the range of 7 to 9% compared to earlier forecasts of a decline of around 15%. PCs and cell phones account for nearly 60% of worldwide semiconductor consumption."
SIA credited economic stimulus programs in China, including incentives for purchasing consumer products and investment in 3G/TDSCDMA communications infrastructure, as having helped drive semiconductor sales in the world’s largest chip market.
“The global macroeconomic environment remains the key factor in determining the timing and rate of recovery for the semiconductor industry,” Scalise concluded.
According to SIA data, sales in the Asia Pacific were up 23.2% in Q2 on a sequential basis. Q2 sales in the Americas were up 11.8% sequentially, while sales in Japan were up 17.9% and sales in Europe were up 0.5%.
Aug 1, 2009
ISDRS'09
The biennial International Semiconductor Device Research Symposium will take place on December 9-11, at the University of Maryland, College Park, Maryland USA.
This Symposium focuses on exploratory research in electronic and photonic materials and devices. Areas such as novel device concepts, processing technologies, advanced modeling, nanotechnology, nanoelectronics, wide band-gap semiconductors, MEMS materials and devices, oxides and dielectrics, magnetic materials and devices, organic and polymer opto-electronic materials and devices, ultra high frequency devices & RF effects, and high power-high temperature devices are included. The Symposium brings together diverse participants in multidisciplinary areas, and provides a forum for extended personal scientific interaction for engineers, scientists, and students working in the field of advanced electronic materials and device technologies.
Moreover, it has a topic dedicated to Compact Modeling, so it can be interesting to go there and have a look.
Extended abstracts from the conference are published online through IEEE Xplore.
Furthermore, presenters may optionally submit a full-length manuscript to be considered for publication in a special issue of Solid State Electronics.
Another interesting advantage of presenting a paper at ISDRS 2009 is that it is held just after IEDM, and very close to the IEDM venue (Baltimore, Maryland), so researchers who present papers at ISDRS can attend before IEDM and then go to ISDRS.
In fact, ISDRS an alternative to IEDM, especially for university teams, in the sense that IEDM is more industrial oriented, while ISDRS focuses more on device properties research and device modeling.
The University of Maryland in College Park is located just 4 miles outside of Washington DC. It is inside of the Capital beltway, accessible by the Washington DC Metro System (green line), and can be reached from all three of the Washington and Baltimore airports.
This Symposium focuses on exploratory research in electronic and photonic materials and devices. Areas such as novel device concepts, processing technologies, advanced modeling, nanotechnology, nanoelectronics, wide band-gap semiconductors, MEMS materials and devices, oxides and dielectrics, magnetic materials and devices, organic and polymer opto-electronic materials and devices, ultra high frequency devices & RF effects, and high power-high temperature devices are included. The Symposium brings together diverse participants in multidisciplinary areas, and provides a forum for extended personal scientific interaction for engineers, scientists, and students working in the field of advanced electronic materials and device technologies.
Moreover, it has a topic dedicated to Compact Modeling, so it can be interesting to go there and have a look.
Extended abstracts from the conference are published online through IEEE Xplore.
Furthermore, presenters may optionally submit a full-length manuscript to be considered for publication in a special issue of Solid State Electronics.
Another interesting advantage of presenting a paper at ISDRS 2009 is that it is held just after IEDM, and very close to the IEDM venue (Baltimore, Maryland), so researchers who present papers at ISDRS can attend before IEDM and then go to ISDRS.
In fact, ISDRS an alternative to IEDM, especially for university teams, in the sense that IEDM is more industrial oriented, while ISDRS focuses more on device properties research and device modeling.
The University of Maryland in College Park is located just 4 miles outside of Washington DC. It is inside of the Capital beltway, accessible by the Washington DC Metro System (green line), and can be reached from all three of the Washington and Baltimore airports.
Jul 26, 2009
Agilent, China University team up on LTE testing
Mike Kawasaki, education program manager at Agilent, said that the company sees the R&D collaboration with Southeast University as a continuation of Agilent's drive to be a key technology partner for innovative research in academia. "This collaboration enables Agilent to make a contribution to the future of wireless communication and gives the university access to our resources, empowering further success of scientists in academia," he said. Read more...
Jul 24, 2009
Postdoctoral Marie Curie Fellowships on Compact Modeling
The European (7th Framework Programme) Call for Postdoctoral Individual Marie Curie Fellowships is open until August 18 2009.
I am looking for one or two candidates to work in my research group at the Universitat Rovira i Virgili (Tarragona, Spain) in the field of compact modeling of advanced semiconductor devices. Therefore, I would like to receive CVs from potential applicants. Once I have selected the candidates, we will make the application.
The candidates must have a Ph D in Electrical Engineering, Electronic Engineering, Physics or Telecommunication Engineering.
There are two open Calls: the one for Intra European Fellowships (FP7-PEOPLE-2009-IEF) and the one for International Incoming Fellowships (FP7-PEOPLE-2009-IIF). Therefore, candidates from European countries can apply for an Intra European Fellowship and candidates from outside Europe can apply for an International Incoming Fellowship.
These felowships can be for one or two years. Salaries are extremely good and the prestige of having this type of fellowship is very high. For this reason, there is a tough competition to get these fellowships.
I am looking for candidates for these Marie Curie Grants, both from Europe and outside Europe. Candidates must have a good CV (preferably with more than 4 publications in international journals, in order to have chances). In order to fit the Marie Curie requirements, their age should be below 35.
If successful, the postdoctoral researchers will work on the characterization of compact modeling of any of the advanced semiconductor devices targeted by our research European projects: nanoscale MOSFETs, SOI and Multi-Gate MOSFETs, strained-Si/SiGe MOSFETs, Schottky-Barrier MOSFETs, nanowire FETs, III-V HEMTs and organic TFTs.
The specific device/s in which the postdoctoral researcher will work will depend on his/her preference and background.
Candidates must send me by e-mail (to benjamin.iniguez@gmail.com) a CV or resume by AUGUST 6. Successful applicants will be informed by August 7, and then we will start to make the application. The successful candidates will be informed on the steps to do.
Tarragona is a small city (110000 inhabitants) on the Mediterranean coast, about 100 Km south from Barcelona, and very well connected to Barcelona and the main Spanish cities by rail and highway. Tarragona is a very old city, very important during the Roman Empire, and with a lot of historical landmarks.
The quality of life in Tarragona is excellent. Mediterranean and mild climate the whole year. Wonderful beaches around the city (even at the city). Mountains close to the city (even the Pyrenees are not far). Besides, the city is very quiet, but with an intense nightlife.
My research group in the Department of Electronic Engineering, Universitat Rovira i Virgili (URV) is one of the strongest groups in compact modeling in Europe. We are leading one European project on compact modeling (in which a total of 15 European universities and companies participate). We also participate on two other European projects (one about nanoscale MOSFETs and another one about organic Thin Film Transistors).
I am looking forward to receiving excellent applications!
Benjamin Iñiguez
Department of Electronic Engineering
Tarragona, SPAIN
Universitat Rovira i Virgili (URV)
E-mail: benjamin.iniguez@gmail.com
I am looking for one or two candidates to work in my research group at the Universitat Rovira i Virgili (Tarragona, Spain) in the field of compact modeling of advanced semiconductor devices. Therefore, I would like to receive CVs from potential applicants. Once I have selected the candidates, we will make the application.
The candidates must have a Ph D in Electrical Engineering, Electronic Engineering, Physics or Telecommunication Engineering.
There are two open Calls: the one for Intra European Fellowships (FP7-PEOPLE-2009-IEF) and the one for International Incoming Fellowships (FP7-PEOPLE-2009-IIF). Therefore, candidates from European countries can apply for an Intra European Fellowship and candidates from outside Europe can apply for an International Incoming Fellowship.
These felowships can be for one or two years. Salaries are extremely good and the prestige of having this type of fellowship is very high. For this reason, there is a tough competition to get these fellowships.
I am looking for candidates for these Marie Curie Grants, both from Europe and outside Europe. Candidates must have a good CV (preferably with more than 4 publications in international journals, in order to have chances). In order to fit the Marie Curie requirements, their age should be below 35.
If successful, the postdoctoral researchers will work on the characterization of compact modeling of any of the advanced semiconductor devices targeted by our research European projects: nanoscale MOSFETs, SOI and Multi-Gate MOSFETs, strained-Si/SiGe MOSFETs, Schottky-Barrier MOSFETs, nanowire FETs, III-V HEMTs and organic TFTs.
The specific device/s in which the postdoctoral researcher will work will depend on his/her preference and background.
Candidates must send me by e-mail (to benjamin.iniguez@gmail.com) a CV or resume by AUGUST 6. Successful applicants will be informed by August 7, and then we will start to make the application. The successful candidates will be informed on the steps to do.
Tarragona is a small city (110000 inhabitants) on the Mediterranean coast, about 100 Km south from Barcelona, and very well connected to Barcelona and the main Spanish cities by rail and highway. Tarragona is a very old city, very important during the Roman Empire, and with a lot of historical landmarks.
The quality of life in Tarragona is excellent. Mediterranean and mild climate the whole year. Wonderful beaches around the city (even at the city). Mountains close to the city (even the Pyrenees are not far). Besides, the city is very quiet, but with an intense nightlife.
My research group in the Department of Electronic Engineering, Universitat Rovira i Virgili (URV) is one of the strongest groups in compact modeling in Europe. We are leading one European project on compact modeling (in which a total of 15 European universities and companies participate). We also participate on two other European projects (one about nanoscale MOSFETs and another one about organic Thin Film Transistors).
I am looking forward to receiving excellent applications!
Benjamin Iñiguez
Department of Electronic Engineering
Tarragona, SPAIN
Universitat Rovira i Virgili (URV)
E-mail: benjamin.iniguez@gmail.com
Papers in IEEE TED, Vol 56 (8), Aug. 2009
Jul 22, 2009
SINANO-NANOSIL Workshop
The SINANO-NANOSIL Workshop will take place in Athens on September 18th, 2008, during the ESSDERC-ESSCIRC Conference.
This Workshop, continuation of the former SINANO Workshop, is a very valuable discussion forum in the area of nanoelectronics devices.
The aim of this Workshop is to present the status and trends of CMOS and beyond-CMOS nanodevices for terascale ICs and to establish a discussion forum in the field of nanoelectronics devices.
The SINANO-NANOSIL Workshop is supported by the SINANO Institute, which is a new European entity created by the main laboratories of the European academic community working in nanoelectronics, and by the European Network of Excellence NANOSIL which targets Silicon-based Nanodevices and is funded by the European Commission for the 7th Framework Programme, from 2008 to 2011. The former SINANO Workshop was funded by the prebvious Network of Excellence, called SINANO.
The program of the SINANO-NANOSIL Workshop consists of several presentations given by a number of representatives of NANOSIL partners:
9:00 Limitations in future gate stack materials
O. Engstrom
Chalmers University
9:30 Metallic source/drain for advanced MOS architectures: from material engineering to device integration
E. Dubois,
IEMN
10:00 Coffee break
10:30 Advanced Memory devices using multi-gate and 3D structures
B. DeSalvo
LETI
11:00 Tunnel FET or Ferroelectric FET to achieve a sub-60mV/decade small swing switch
A. Ionescu
EPFL
11:30 Electron Transport in Graphene Quantum Dots and Quantum Point Contacts
L. Ponomarenko
University of Manchester
12:00 Lunch
13:30 Variability in Nanoscale CMOS and Nanowires
A. Asenov
University of Glasgow
14:00 Simulation of gate leakage currents in UTB MOSFETs and Nanowires
A. Schenk,
ETH-Zentrum
14:30 3D quantum transport simulations of Si Nanowires: impact of elastic and inelastic scattering
M. Pala
IMEP-LAHC, Grenoble INP-Minatec
15:00 Deterministic solution of the 1D Boltzmann transport equation
G. Baccarani, E. Gnani, A. Gnudi and S. Reggiani
ARCES-IUNET
15:30 End of the Workshop
This Workshop, continuation of the former SINANO Workshop, is a very valuable discussion forum in the area of nanoelectronics devices.
The aim of this Workshop is to present the status and trends of CMOS and beyond-CMOS nanodevices for terascale ICs and to establish a discussion forum in the field of nanoelectronics devices.
The SINANO-NANOSIL Workshop is supported by the SINANO Institute, which is a new European entity created by the main laboratories of the European academic community working in nanoelectronics, and by the European Network of Excellence NANOSIL which targets Silicon-based Nanodevices and is funded by the European Commission for the 7th Framework Programme, from 2008 to 2011. The former SINANO Workshop was funded by the prebvious Network of Excellence, called SINANO.
The program of the SINANO-NANOSIL Workshop consists of several presentations given by a number of representatives of NANOSIL partners:
9:00 Limitations in future gate stack materials
O. Engstrom
Chalmers University
9:30 Metallic source/drain for advanced MOS architectures: from material engineering to device integration
E. Dubois,
IEMN
10:00 Coffee break
10:30 Advanced Memory devices using multi-gate and 3D structures
B. DeSalvo
LETI
11:00 Tunnel FET or Ferroelectric FET to achieve a sub-60mV/decade small swing switch
A. Ionescu
EPFL
11:30 Electron Transport in Graphene Quantum Dots and Quantum Point Contacts
L. Ponomarenko
University of Manchester
12:00 Lunch
13:30 Variability in Nanoscale CMOS and Nanowires
A. Asenov
University of Glasgow
14:00 Simulation of gate leakage currents in UTB MOSFETs and Nanowires
A. Schenk,
ETH-Zentrum
14:30 3D quantum transport simulations of Si Nanowires: impact of elastic and inelastic scattering
M. Pala
IMEP-LAHC, Grenoble INP-Minatec
15:00 Deterministic solution of the 1D Boltzmann transport equation
G. Baccarani, E. Gnani, A. Gnudi and S. Reggiani
ARCES-IUNET
15:30 End of the Workshop
9:00 Limitations in future gate stack materials
O. Engstrom
Chalmers University
9:30 Metallic source/drain for advanced MOS architectures: from material engineering to device integration
E. Dubois,
IEMN
10:00 Coffee break
10:30 Advanced Memory devices using multi-gate and 3D structures
B. DeSalvo
LETI
11:00 Tunnel FET or Ferroelectric FET to achieve a sub-60mV/decade small swing switch
A. Ionescu
EPFL
11:30 Electron Transport in Graphene Quantum Dots and Quantum Point Contacts
L. Ponomarenko
University of Manchester
12:00 Lunch
13:30 Variability in Nanoscale CMOS and Nanowires
A. Asenov
University of Glasgow
14:00 Simulation of gate leakage currents in UTB MOSFETs and Nanowires
A. Schenk,
ETH-Zentrum
14:30 3D quantum transport simulations of Si Nanowires: impact of elastic and inelastic scattering
M. Pala
IMEP-LAHC, Grenoble INP-Minatec
15:00 Deterministic solution of the 1D Boltzmann transport equation
G. Baccarani, E. Gnani, A. Gnudi and S. Reggiani
ARCES-IUNET
15:30 End of the Workshop
O. Engstrom
Chalmers University
9:30 Metallic source/drain for advanced MOS architectures: from material engineering to device integration
E. Dubois,
IEMN
10:00 Coffee break
10:30 Advanced Memory devices using multi-gate and 3D structures
B. DeSalvo
LETI
11:00 Tunnel FET or Ferroelectric FET to achieve a sub-60mV/decade small swing switch
A. Ionescu
EPFL
11:30 Electron Transport in Graphene Quantum Dots and Quantum Point Contacts
L. Ponomarenko
University of Manchester
12:00 Lunch
13:30 Variability in Nanoscale CMOS and Nanowires
A. Asenov
University of Glasgow
14:00 Simulation of gate leakage currents in UTB MOSFETs and Nanowires
A. Schenk,
ETH-Zentrum
14:30 3D quantum transport simulations of Si Nanowires: impact of elastic and inelastic scattering
M. Pala
IMEP-LAHC, Grenoble INP-Minatec
15:00 Deterministic solution of the 1D Boltzmann transport equation
G. Baccarani, E. Gnani, A. Gnudi and S. Reggiani
ARCES-IUNET
15:30 End of the Workshop
ESSCIRC/ESSDERC early registration deadline ***26/7/2009***
Some information from Matthias Bucher
Dear Colleagues,
Please let me draw your attention to the deadline for early registration for ESSDERC/ESSCIRC 2009 in Athens, 14-18/9/2009, is this Sunday, 26 July. For those who have not registered yet, consider the reduced registration fees, http://www.esscirc2009.org/?pid=3.
I also would like to draw your attention to the Tutorials on Monday 14/9/2009, http://www.esscirc2009.org/?pid=7. Of course you are aware the MOS-AK workshop is held on Friday 18/9/2009, please **do** register as well! (even though it is free, and even for those of you who might not attend ESSDERC/ESSCIRC).
As an additional information, I’m attaching below some links to hotels that you might want to consider booking, in the Acropolis and Plaka region, about 20-25 minutes (either metro and/or walking) or 15 minutes by taxi, from the Caravel hotel where the conference is held. Hotels very close to the Caravel are probably already booked (those indicated on the conference site) or very expensive (Hilton, and Caravel). Don't delay booking, I hope these are of some help.
Acropolis Museum Boutique hotel, 48 Sygrou Ave., 11720 Athens
http://www.booking.com/hotel/gr/acropolis-museum-boutique.en.html?sid=86c27c055ff3d2b31320a517ff769305
Airotel Parthenon, 6 Makri Str., 11742 Athens
http://www.booking.com/hotel/gr/parthenon.en.html?sid=86c27c055ff3d2b31320a517ff769305
Acropolis Select Hotel, 37-39 Falirou Str., 11742 Athens
http://www.tripadvisor.com/Hotel_Review-g189400-d230390-Reviews-Acropolis_Select_Hotel-Athens_Attica.html
or hotels in the "Plaka" area (again close to Acropolis and close to metro stations)
Amazon Hotel, Mitropoleos 19 & Pentelis 7, 10557 Athens
http://www.booking.com/hotel/gr/amazonathens.html
PLAKA HOTEL ATHENS, 7 Kapnikareas & Mitropoleos, Athens
http://www.holiday-in-athens.com/athens/plaka-hotel-athens.html
Jul 17, 2009
Post-Silicon Solutions Emerging
Post-Silicon Solutions Emerging:
Researchers have an array of new technologies in the pipeline to boost CMOS logic and memory performance, Sematech Vice President Raj Jammy said Tuesday at the Device Scaling TechXPOT at SEMICON West. High-mobility graphene channels, gates built around nanowires, finFETs with III-V materials -- all promise to blow past the power/performance capabilities of silicon CMOS.
David Lammers, News Editor -- Semiconductor International, 7/15/2009
Researchers have an array of new technologies in the pipeline to boost CMOS logic and memory performance, Sematech Vice President Raj Jammy said Tuesday at the Device Scaling TechXPOT at SEMICON West.
 |
| "We need disruptive materials and technologies," said Raj Jammy of Sematech. |
High-mobility graphene channels, gates built around nanowires, finFETs with III-V materials -- all promise to blow past the power/performance capabilities of silicon CMOS. Jammy, in charge of materials and emerging technologies research at Sematech, warned that "people entrenched in the silicon world" may need to rethink as scaling of today's CMOS transistors becomes increasingly difficult.
"We need disruptive materials and technologies," Jammy said, describing R&D progress on several post-22 nm options. Progress is being made on heterogeneous devices, where germanium is used as the channel in the pFET and indium gallium arsenide (InGaAs), for example, on the nFET. Nanowires with a gate-all-around design are drawing more R&D attention, and work continues on finFETs -- vertical structures that allow better control of the channel.
Memory R&D is equally vibrant. For decades, mainstream memories have been based on charge storage. "But when you make these devices really small, charge storage is no longer possible." On the horizon are phase change memories (PCRAMs) and metallic resistive RAMs (ReRAMs), though Jammy acknowledged that the question regarding ReRAM technology is: "Does it work at less than 20 nm?"
Also under study are zero-leakage nanoelectrical-mechanical system (NEMS) devices, which Jammy said "exhibit instant on and off." And because they are mechanical, they can safely operate in hazardous environments, such as a nuclear power plant.
 |
| Schubert Chu of Applied Materials spoke of the potential of carbon-doped silicon for nFET strain. |
Schubert Chu, an Applied Materials product manager for epi/LPCVD products, examined the possibility of embedded silicon carbon (eSiC) being used to enhance the performance of the nFET. While embedded silicon germanium (eSiGe) has served to effectively strain the pFET, SiC has been a tougher challenge, largely because the carbon atoms tend to move around.
Chu said that an AMD-led team has shown a 30% improvement with nFETs strained by SiC structures. "Silicon carbon is on track to be adopted at the 22 nm generation."
SiGe stressors face challenges as the germanium content moves from 25-30% at the 45 nm node to >40% at the 22 nm node. Applied Materials has developed a "Siconi" pre-clean option for its Centura epitaxial deposition tool, which Chu said will extend epi strain technologies.
Jammy said the industry faces serious cost challenges. "When we hear that it may cost $80M for a EUV scanner, we are not going in the right direction on costs," he said.Organic semiconductor researchers honoured by Institute of Physics
From the OSADirect Newsleter:
The 2009 Faraday Medal, one of the Institute's three gold medals, has been awarded to Professor Donal Bradley FRS for his pioneering work in the field of plastic electronics. Professor Bradley who holds the Lee Lucas Chair in Experimental Physics, is Director of the newly established Centre for Plastic Electronics at Imperial.
Professor Bradley's research focuses on optimising plastic semiconductors for use in a wide range of electronic devices, with applications spanning displays, lighting, electronics, solar energy, communications and medical diagnostics.
Professor Bradley said, "What a wonderful way to celebrate the twentieth anniversary of conjugated polymer LEDs - a discovery that helped to launch plastic electronics on the path to its present day vibrancy as an academic research field with great commercial potential. I am delighted to have been able to walk that path in the company of so many talented students, postdoctoral researchers and academic and industrial colleagues – this award recognises the fruits of a great many, very enjoyable collaborative interactions."
Professor Jenny Nelson has been awarded the Joule Medal. Prof. Nelson is currently working on the use of molecular or 'plastic' electronic materials in solar cells, in order to reduce the cost of solar electricity. Once the basic properties of the materials are properly understood, design rules can be developed for new materials and types of device with better performance.
20th Anniversary of Innovation
View from The Top Executive Interviews "20th Anniversary of Innovation", John Tanner, CEO Tanner EDA Follow audio interview...
Lynguent Debuts Radiation Hardened By Design, BSIM4 Compact Model Toolkits
Lynguent®, Inc., announced two new toolkits for its ModLyng[tm] Integrated Modeling Environment (IME): Radiation Hardened By Design (RHBD) Toolkit and BSIM4 Compact Model Toolkit. The RHBD Toolkit includes models and tools which provide a modeling and analysis capability for Single Event Upset (SEU) behaviors in deep sub-micro processes. The BSIM4 Compact Model Toolkit includes a high fidelity BSIM4 model which provides more flexibility than has ever been available for adding new effects to existing processes built upon the BSIM foundation. These toolkits, when used with the ModLyng IME, enable semiconductor and systems companies to easily enhance their IC design flows with radiation SEU capability and thus save weeks in qualifying their designs and cell libraries for radiation hardness.
Read more...
Read more...
Jul 7, 2009
New Book:
Compact MOSFET Models for VLSI Design
A. B. Bhattacharyya
ISBN: 978-0-470-82342-2
Hardcover 512 pages April 2009
This book is essential for students specializing in VLSI Design and indispensible for design professionals in the microelectronics and VLSI industries. Written to serve a number of experience levels, it can be used either as a course textbook or practitioner’s reference. Read more...
Access the MATLAB code, solution manual, and lecture materials at the companion website.
Jul 3, 2009
IC Insights expects an 18% "surge" in the IC market
I post here a very interesting article, even if not related to compact modelling, from EDN:(visit them for more interesting articles)
IC market second-half 'surge' predicted
IC Insights expects an 18% "surge" in the IC market in the second half of the year and claims there is clear evidence that the much-anticipated turning point toward recovery has already occurred.
By Suzanne Deffree, Managing Editor, News -- Electronic News, 7/2/2009
The second half of 2009 will be much better than the first for the semiconductor industry, and will be marked by an IC market "surge," according to IC Insights.
The market research company this week reported that while the first half of 2009 was hit hard by seasonal weakness for electronic system sales, a major IC inventory adjustment, and the global recession at its worst, the second half of 2009 is expected to usher in strong seasonal strength for electronic system sales, a period of IC inventory replenishment, and positive worldwide GDP growth.
"In IC Insights' opinion, the bottom of the current cycle in the worldwide economy and semiconductor industry was reached in Q1 2009," Bill McClean, president of IC Insights, said in a statement on the company's mid-year update. "While the 'velocity' of the semiconductor industry recovery is subject to debate (slow, moderate, fast, etc), at least the discussion over the next few quarters will be about how much sequential growth can be expected in instead of how far the markets are going to fall."
|
For example, according to the company's data, worldwide GDP growth is forecast to be negative this year of down 0.8% on a weak first half with growth down, but the second half of the year is expected to register positive growth of 2%. (See figure 1 below.) The same pattern is forecast for the US economy, as well, with the second half showing growth of 1.3% as compared to the first half.
Specific to the electronics industry, IC Insights reported seasonal strength is likely to propel second-half cell phone and PC unit shipments up by 18% and 15%, respectively, as compared to the first half.
Overall, IC Insights said it expects an 18% "surge" in IC market sales in the second half, as compared to the first half. "In fact, the double-digit Q2 2009/Q1 2009 IC market increase is clear evidence of the fact that the much-anticipated turning point has already occurred," McClean said.
According to IC Insights, the IC foundry market is expected to continue its "sharp recovery" in the second half of 2009. McClean noted that the IC foundry market almost doubled in Q2 as compared to Q1.
"There is no doubt that, as a group, the semiconductor equipment suppliers have taken the worst 'beating' of any of the companies involved in the current semiconductor industry downturn," McClean said. "However, the second half of 2009 is expected to offer some relief for these suppliers as semiconductor industry capital spending is forecast to jump by 28% as compared to the first half of 2009."
McClean noted that many of the major semiconductor suppliers that IC Insights tracks are planning to spend the majority of their capital spending budgets in the second half of 2009. Offering example, he said Hynix spent 30% of its 2009 spending budget in the first half, but plans to spend the remaining 70% in the second half.
Jun 30, 2009
Old glories never die... do they?
It's quite hard for an old glory like HSPICE to die. See the post in aboutSpice.com:
SMIC Deploys Synopsys HSPICE Simulator for 45-nm Physical IP and Standard Cell Development (Synopsys)
Have a nice summertime!
SMIC Deploys Synopsys HSPICE Simulator for 45-nm Physical IP and Standard Cell Development (Synopsys)
Have a nice summertim
Publicar entrada
Jun 18, 2009
An Insider’s View to the Swiss LP/LV CMOS Design History
Organizers: Jean-Michel Sallese; EPFL and Wladek Grabinski; GMC Consulting
Host: Predrag Habas; EM Marin
Where: EPFL - Swiss Federal Institute of Technology, Lausanne, Room CO017
When: Friday, July 3, 2009, 5:00 pm
Title: An Insider’s View to the Swiss LP/LV CMOS Design History
Presenter: Stefan Cserveny
Host: Predrag Habas; EM Marin
Where: EPFL - Swiss Federal Institute of Technology, Lausanne, Room CO017
When: Friday, July 3, 2009, 5:00 pm
Title: An Insider’s View to the Swiss LP/LV CMOS Design History
Presenter: Stefan Cserveny
Abstract: I worked the last 30 years at CEH - CSEM, the amazing Swiss crucible at the origin of the very low power integrated circuits, taking advantage of its highly professional, creative and enthusiastic teams and the close and fruitful collaboration with the EPFL and the Swiss industry. I will present some of these historical developments as viewed by the subjects in which I had the opportunity to add my contribution. After a short overview of my background and work done before joining the CEH, I will first present the early compact MOS modeling work done in order to satisfy the requirements for the LP/LV design including the near threshold range - a work setting the path towards the presently largely used EKV model. The following items are some of the sensor interface circuits, the realization of embedded low power non-volatile memories and, finally, the very low leakage SRAM memories essential for many critical applications.
Short Bio: Stefan Cserveny is retiring after 47 years of teaching and research and development activities as an electron device engineer and as a circuit designer, especially for designs requiring device expertise. The first 17 years he lectured electron devices and circuits at the Polytechnic Institute of Bucharest, Romania and at the Telecommunication Institute of Oran, Algeria, which he helped to create, writing several textbooks and scientific papers. In 1972 he obtained a one year specialization grant he spent at the University of California Berkeley where he received the M.S. degree in electrical engineering. In 1979 he joined the 17 years old CEH, which in 1984 became part of CSEM, getting involved with the LP/LV challenge first needed for the watch industry. In his position of scientific expert he contributed to research projects and ASIC developments; most interesting results have been published. He also participated in the BCTM technical program committee, reviewed a large number of papers and did consulting for Swiss companies.
QUCS developments
The QUCS development team is taking part in the MOS Modelling and Extraction Working Group (MOS-AK) Verilog-A standardisation initiative.
Read more...
The QUCS Team is also contributing to the MIXDES special session "Device Level Support for Emerging CMOS Technologies" organised by Daniel Tomaszewski; ITE, Poland and Wladek Grabiński; GMC Suisse (with MOS-AK/GSA Group and COMON EU Project coordination)
Read the QUCS paper's abstract: "Compact Device Modeling for Established and Emerging Technologies with the Qucs GPL Circuit Simulator"
Read more...
The QUCS Team is also contributing to the MIXDES special session "Device Level Support for Emerging CMOS Technologies" organised by Daniel Tomaszewski; ITE, Poland and Wladek Grabiński; GMC Suisse (with MOS-AK/GSA Group and COMON EU Project coordination)
Read the QUCS paper's abstract: "Compact Device Modeling for Established and Emerging Technologies with the Qucs GPL Circuit Simulator"
Future Solutions of System On Chip (SoC)
Frédéric Boeuf, Principal Engineer at STM, gave a short course at the VLSI Symposium 2009 in Kyoto. It is a synthesis on the silicon technology uses for system on chip applications, and some prospect about the future solutions.
View the slide presentation...
View the slide presentation...
Jun 12, 2009
IMEC Tips 10 nm Options at Tech Forum
I copy a post from Semiconductor International:
IMEC Tips 10 nm Options at Tech Forum: "At the IMEC Technology Forum in Brussels, Belgium, IMEC Fellow Marc Heyns presented various CMOS transistor possibilities for 15 nm and beyond. "We are at the brink of a new era of innovation," Heyns said, adding that he sees no fundamental barriers to scaling to the 10 nm node. One roadmap involves the integration of new materials and structures over time..."
(read more)
IMEC Tips 10 nm Options at Tech Forum: "At the IMEC Technology Forum in Brussels, Belgium, IMEC Fellow Marc Heyns presented various CMOS transistor possibilities for 15 nm and beyond. "We are at the brink of a new era of innovation," Heyns said, adding that he sees no fundamental barriers to scaling to the 10 nm node. One roadmap involves the integration of new materials and structures over time..."
(read more)
MNE'09 in Ghent
The 35th International Conference on Micro & Nano Engineering (MNE), to be held in Ghent, Belgium from 28 September to 1 October 2009.
The scope is about micro- and nano-fabrication and manufacturing using lithography and other nano-patterning related approaches. The conference brings together engineers and scientists from all over the world to discuss recent progress and future trends in the fabrication, manufacturing and application of micro-and nano-structures and devices. Applications in electronics, electromechanics, environment and life sciences are discussed such as: nanoelectronics, MEMS-NEMS, bioMEMS and lab-on-a-chip devices.
Read more...
The scope is about micro- and nano-fabrication and manufacturing using lithography and other nano-patterning related approaches. The conference brings together engineers and scientists from all over the world to discuss recent progress and future trends in the fabrication, manufacturing and application of micro-and nano-structures and devices. Applications in electronics, electromechanics, environment and life sciences are discussed such as: nanoelectronics, MEMS-NEMS, bioMEMS and lab-on-a-chip devices.
Read more...
Jun 10, 2009
International Workshop on Compact Thin-Film Transistor (TFT) Modeling for Circuit Simulation
The Second International Workshop on Compact Thin-Film Transistor (TFT) Modeling for Circuit Simulation will be held at the University College London (UCL) in London (UK) on September 25 2009.
This workshop is intended to provide a forum for discussions and current practices on compact TFT modeling. The workshop is sponsored by IEEE EDS Compact Modeling Technical Committee in collaboration with IEEE UCL-Cambridge University EDS/LEOS Chapter joint chapter that is in the process of formation. Topics include include:
• Physics of TFTs and operating principles
• Compact TFT device models for circuit simulation
• Model implementation and circuit analysis techniques
• Model parameter extraction techniques
• Applications of compact TFT models in emerging products
• Compact models for interconnects in active matrix flat panels
The deadline for Abstract Submission is July 15 2009.
Prospective authors should submit a 500-word abstract to: m.bauza@ucl.ac.uk
If their abstract is accepted, the authors will be invited to submit of a 4-page paper to be included in proceedings. The deadline is August 15, 2009.
This is the only workshop especifically devoted to the compact modeling of TFT!
Jun 9, 2009
Compact modeling postdoc position at Institute of Electron Technology (Warsaw, Poland)
The Division of Silicon Microsystem and Nanostructure (http://www.ite.waw.pl/en/Z02.php) at Institute of Electron Technology (http://www.ite.waw.pl/en/index.php), Warsaw, Poland is seeking an experienced researcher for a position in the frame of a European Marie Curie Project.
Area of work
The researcher will work in the area of compact modelling of multi-gate MOSFETs. Two main topics should be covered during the researcher stay in ITE:
- development of parameter extraction methods for multi-gate MOS devices, using I-V, C-V, G-V characteristics of sets of devices, and based on combination of global optimization (constrained or unconstrained) and local fitting approaches,
- development of parameter extraction methods based on electrical characteristics of sets of multi-gate MOS devices, which account for parameters fluctuations within a wafer; (example: extraction of MOSFETs size variations DW, DL due to systematic and/or statistic photolithography and other processes fluctuations).
The work will be done in collaboration with a leading European semiconductor foundry, and leading modelling and characterization groups from European universities.
Contract details
Temporary contract, duration 20 months, full time, starting date 1 October 2009. This postdoc post is funded by the Marie-Curie European Compact Modelling network. The net monthly salary is more than 2200 Euro/month.
Application deadline: 31 August 2009.
Contact: Dr. Daniel Tomaszewski, email: dtomasz@ite.waw.pl
Requirements
Candidates should possess either
- a Ph.D. degree or
- a M.Sc. or Dipl.-Ing. Degree and at least 4 years of research experience
in electrical engineering, preferably in semiconductor microelectronics.
Good skills in written and spoken English are mandatory.
Desirable is research experience in the following areas:
- Compact modeling of MOS devices
- Characterization methods of MOS devices
- Numerical simulation of MOS devices
- Numerical methods
- Programming
Area of work
The researcher will work in the area of compact modelling of multi-gate MOSFETs. Two main topics should be covered during the researcher stay in ITE:
- development of parameter extraction methods for multi-gate MOS devices, using I-V, C-V, G-V characteristics of sets of devices, and based on combination of global optimization (constrained or unconstrained) and local fitting approaches,
- development of parameter extraction methods based on electrical characteristics of sets of multi-gate MOS devices, which account for parameters fluctuations within a wafer; (example: extraction of MOSFETs size variations DW, DL due to systematic and/or statistic photolithography and other processes fluctuations).
The work will be done in collaboration with a leading European semiconductor foundry, and leading modelling and characterization groups from European universities.
Contract details
Temporary contract, duration 20 months, full time, starting date 1 October 2009. This postdoc post is funded by the Marie-Curie European Compact Modelling network. The net monthly salary is more than 2200 Euro/month.
Application deadline: 31 August 2009.
Contact: Dr. Daniel Tomaszewski, email: dtomasz@ite.waw.pl
Requirements
Candidates should possess either
- a Ph.D. degree or
- a M.Sc. or Dipl.-Ing. Degree and at least 4 years of research experience
in electrical engineering, preferably in semiconductor microelectronics.
Good skills in written and spoken English are mandatory.
Desirable is research experience in the following areas:
- Compact modeling of MOS devices
- Characterization methods of MOS devices
- Numerical simulation of MOS devices
- Numerical methods
- Programming
Jun 8, 2009
Compact Modeling Job Vacancy at Technical University Ilmenau, Germany
The RF & Nano Device group (http://www.tu-ilmenau.de/fakei/1342+M54099f70862.0.html) at TU Ilmenau (http://www.tu-ilmenau.de/uni/index.php) is seeking an experienced researcher for a position in the frame of a European Marie Curie Project.
The researcher will work on compact modeling of high-frequency transistors, in
particular HEMTs (High Electron Mobility Transistor). He or she will be responsible
for the development of compact models for the large-signal high-frequency behavior of
HEMTs. This will include models for the dc current-voltage characteristics and the high-frequency large-signal behavior of HEMTs with special emphasis on the modeling of nonlinearities including the extraction of model parameters from experimental results. The work will be done in close contact to a leading European semiconductor foundry.
Contract details: Temporary contract, duration 20 months, full time, starting date 1 September 2009.
Application deadline: 31 July 2009.
Contact: PD Dr. Frank Schwierz, email: frank.schwierz@tu-ilmenau.de
Requirements: Candidates should possess either
- a Ph.D. degree or
- a Master or Dipl.-Ing. Degree and at least 4 years of research experience
in electrical engineering, preferably in semiconductor electronics. Good skills in written and spoken English are mandatory.
Desirable is research experience in the following areas:
- Compact modeling of semiconductor devices
- Large-signal modeling and analysis
- Nonlinear behavior of semiconductor devices and modeling of nonlinearities.
The researcher will work on compact modeling of high-frequency transistors, in
particular HEMTs (High Electron Mobility Transistor). He or she will be responsible
for the development of compact models for the large-signal high-frequency behavior of
HEMTs. This will include models for the dc current-voltage characteristics and the high-frequency large-signal behavior of HEMTs with special emphasis on the modeling of nonlinearities including the extraction of model parameters from experimental results. The work will be done in close contact to a leading European semiconductor foundry.
Contract details: Temporary contract, duration 20 months, full time, starting date 1 September 2009.
Application deadline: 31 July 2009.
Contact: PD Dr. Frank Schwierz, email: frank.schwierz@tu-ilmenau.de
Requirements: Candidates should possess either
- a Ph.D. degree or
- a Master or Dipl.-Ing. Degree and at least 4 years of research experience
in electrical engineering, preferably in semiconductor electronics. Good skills in written and spoken English are mandatory.
Desirable is research experience in the following areas:
- Compact modeling of semiconductor devices
- Large-signal modeling and analysis
- Nonlinear behavior of semiconductor devices and modeling of nonlinearities.
Jun 4, 2009
IEEE SCV EDS Electron Device talks for June
"Negative Bias Temperature Instability in p-MOSFETs: Fundamentals, Characterization, Materials Dependence and Modeling"
Speaker: Dr. Souvik Mahapatra, Dept. of Electrical Engineering, IIT Bombay
Date: Tuesday, June. 9, 2009
Location: National Semiconductor, Building E1, Conference Center, 2900 Semiconductor Drive, Santa Clara, CA 95051.
More information at the IEEE Santa Clara Valley EDS Chapter Home Page.
Speaker: Dr. Souvik Mahapatra, Dept. of Electrical Engineering, IIT Bombay
Date: Tuesday, June. 9, 2009
Location: National Semiconductor, Building E1, Conference Center, 2900 Semiconductor Drive, Santa Clara, CA 95051.
More information at the IEEE Santa Clara Valley EDS Chapter Home Page.
Jun 3, 2009
Job offers
Three nice job offers:
Microwave Device Modeling Engineer, Massachusetts
Device Modeling Engineer, Cambridgeshire
Device Simulation Engineer - Solar, Surrey
Remember that we only post these offers here as an act of good will, and we're not related in any form to any of them...
Microwave Device Modeling Engineer, Massachusetts
Device Modeling Engineer, Cambridgeshire
Device Simulation Engineer - Solar, Surrey
Remember that we only post these offers here as an act of good will, and we're not related in any form to any of them...
May 29, 2009
Agilent-EEsof X-Parameters Course
Agilent-EEsof is offering an 3-day course – July 7-9 (Massy – France)
WHAT WILL YOU LEARN?
Read more...
WHAT WILL YOU LEARN?
- This course starts with an overview of non-linear components behavioral modeling and the extension of S-parameters into X-parameters.
- Then it drives you through the calibration requirements for X-parameters measurements. Finally the use of X-parameters models in ADS (Advanced Design System) is illustrated with cascaded amplifiers in an LTE (3rd Gen. Partnership Project - Long Term Evolution) RF subsystem.
- Participants will have the opportunity to drive the measurements and perform hands-on exercises in the ADS software.
Read more...
Organic, Molecular and Nanostructured Electronics - Physics and Technology
Date: June 8-12, 2009 | Continuing Education Units
Description: This course will review basic concepts underlying the design, fabrication, and operation of three dominant types of organic electronic devices: light emitting devices (OLEDs), photosensitive devices (solar cells and photodetectors), and field effect transistors (OFETs). We will also discuss, but devote less time to, organic lasers, organic memories, and chemical sensors. The course aims to present a broad and practical survey of the field and to immerse you in the broad field of organic materials. As a sub-class of nanostructured solids, organic thin films exemplify challenges of the practical nanotechnologies. Many concepts presented in the class are directly transferable to a broader field of nanostructured materials.
Instructors: Professors Vladimir Bulovic and Marc Baldo of the MIT Laboratory of Organic Optics and Electronics.
Read More...
Description: This course will review basic concepts underlying the design, fabrication, and operation of three dominant types of organic electronic devices: light emitting devices (OLEDs), photosensitive devices (solar cells and photodetectors), and field effect transistors (OFETs). We will also discuss, but devote less time to, organic lasers, organic memories, and chemical sensors. The course aims to present a broad and practical survey of the field and to immerse you in the broad field of organic materials. As a sub-class of nanostructured solids, organic thin films exemplify challenges of the practical nanotechnologies. Many concepts presented in the class are directly transferable to a broader field of nanostructured materials.
Instructors: Professors Vladimir Bulovic and Marc Baldo of the MIT Laboratory of Organic Optics and Electronics.
Read More...
International Summer School MOMiNE 2009
International Summer School on Modelling and Optimization in Micro- and Nano- Electronics - MOMiNE Italy Sept. 2009: The aim of the School is to stimulate intensive transfer of knowledge and discussion on modeling and optimization of electronic circuits and devices, by presenting the latest developments, insights, methods, algorithms and ideas in these areas of research, providing also indications for future research directions. An important aspect is the involvement of researchers working for industries, which can provide a more timely indication of the most relevant up-to-date problems encountered in real industrial environments.
The International Summer School MOMINE 2009 will be held from 31/08 to 12/09 at:
Grand Hotel San Michele
Località: Bosco 8/9, 87022 Cetraro (Cosenza), Italy
Phone: (+39) 0982 91012 Fax: (+39) 0982 91430
Read more...
The International Summer School MOMINE 2009 will be held from 31/08 to 12/09 at:
Grand Hotel San Michele
Località: Bosco 8/9, 87022 Cetraro (Cosenza), Italy
Phone: (+39) 0982 91012 Fax: (+39) 0982 91430
Read more...
May 28, 2009
Graduate Student Meeting on Electronic Engineering
The Graduated Student Meeting on Electronic Engineering (formerly Nanoelectronics and Photonics Systems Workshop), has been an annual event, created and organized by the Universitat Rovira i Virgili (URV), in Tarragona (Catalonia, Spain) since 2003. It consists of two days of plenary talks given by invited prestigious researchers (from different countries) about selected topics related to electronic engineering and two poster sessions were PhD students in this field will present their work.
This Graduated Student Meeting has become a very useful forum for PhD students and researchers in the field of Electronic Engineering. The present edition will take place in June 19th and 20th.
This year, the Graduated Student Meeting is being sponsored by the NANOSIL European Network of Excellence.
Awards for the best student paper/posters in two categories: one category for Master students and another category for Doctoral Students.
2-pages abstracts corresponding to paper or poster presentations and plenary talks will be published in the Proceedings. The deadline for abstracts reception is June 8th.
The plenary talks will be given by the following lecturers:
Prof Juin J Liou. University of Central Florida, Orlando, FL (USA). "Protecting Microchips agains Electrostatic Discharge (ESD) Shock."
Dr Michele Penza. Italian Agency for New Technologies, Energy and Environment.
Department of Physical technologies and new materials. Research Center Brindisi (Italy). "Carbon nanotube gas sensors: chemiresistors and SAW devices."
Prof. Ettore Napoli. Department of Electronic and Telecommunication Engineering. University of Naples Federico II (Italy). "Superjunction power devices".
Dr Denis Buttard. CEA-GrenobleLaboratoire de Silicium Nanoélectronique Photonique et StructuresINAC/SP2M/SiNaPSMINATEC-BCA. 38054 Grenoble Cedex 9 (France). "Elaboration and structural investigation of the confined growth of silicon nanowires in a nanoporous matrix: application to phovoltaic cell".
Prof. Yuhua Cheng. Shanghai Research Institute of Microelectronics, Peking University (China). "Design-for-Manufacturing in Nano-CMOS Era."
Dr. Daniela Iacopino. Nanotechnology Group. Tyndall National Institute. Cork (Ireland).
"Nanocrystal-Molecule Nanostructures: Formation, Plasmonic Properties & Electrical Contacting"
Tarragona is located in the south of Catalonia, in the northeast corner of the Iberian Peninsula.
Tarraco (the Roman name for Tarragona) was one of the most important cities in the Roman Empire. On 30 November 2000, the UNESCO committee officially declared the Roman archaeological complex of Tàrraco a World Heritage Site. This recognition is intended to help ensure the conservation of the monuments, as well as to introduce them to the broader international public.
In June the weather is warm enough to go to the beaches in or around Tarragona, but comfortable enough to walk and do sightseeing in the city. Thanks to its Mediterranean climate, its clean beaches with fine and gloden sand, and its singular artistic and architectural heritage, Tarragona is one of the most important tourism hubs in Europe.
I encourage Ph D students to send abstracts and attend this interesting Meeting!
Job offer in Compact Modelling - 28 May 2009
I post here a job offer from LinkedIn, I think it may be of interest for many of you, dearest readers.... Please remember that we only copy here the offer, and that we are not related in any way to those offering the position!!
In case you are interested, kindly pass your CV immediately to gopal.svks@gmail.com / gopal@svcircuit.com
Senior Manager/Manager -Analog-RF,AMS–Malaysia
Exp-PhD / Master with 10+ , candidate should be solid in Analog,RF characterization, SPICE & compact modeling for high voltage MOS, BJT, BCD devices
In case you are interested, kindly pass your CV immediately to gopal.svks@gmail.com / gopal@svcircuit.com
Senior Manager/Manager -Analog-RF,AMS–Malaysia
Exp-PhD / Master with 10+ , candidate should be solid in Analog,RF characterization, SPICE & compact modeling for high voltage MOS, BJT, BCD devices
Placement location –Malaysia
Position -- very urgent and need to be filled ASAP.
Interview - 2weeks altogether.
Package – Will be the best in the semiconductor industry
Type -Full time and permanent with our client..
Malaysia Responsibilities:
• Lead a team of engineers to provide Integrated Circuit Design Technology solutions.
• Supervise test-chip design for "Client" technology characterization, SPICE model generation
for RF, Analog and mixed signal active and passive devices, and development of process design
kit (PDK) for "Client" technologies.
• Review, update, and manage electrical design rule (EDR) specifications for all "Client"
technologies – accuracy and availability of up-to-date revision.
• Interface with "Client" technology development (TD), customer engineering (CE), and Fab
engineering departments to support technology development, customer support, and
manufacturing, respectively.
• Interact with marketing group to provide modeling solutions to "Client" customers.
• Follow and comply with the procedures and by-laws of "Client" Environmental Management
System (EMS).
• Review all environmental objectives, targets, and plans and ensure their implementation in
accordance to the requirements set by "Client" EMS.
Requirements:
• 10+ years of experience in managing integrated circuit Design Technology including design rule
generation, device characterization and compact modeling and industry best practices.
• Extensive knowledge of compact modeling for Analog/RF and mixed-signal technologies
including high voltage MOS, BJT, BCD devices for circuit simulation.
• Extensive knowledge of integrated passive and active components characterization and modeling.
• Good verbal/written communication skills and proven ability to work in and lead cross functional
teams.
• Proven leadership and management skills in high technology industry.
• M.S. or PhD in Electrical Engineering, Physics, or related technical fields with > 10 years relevant
experience in logic, Analog/RF, and mixed-signal device & interconnect modeling as well as CAD
to support customer design.
• Working experience in TCAD device design is added advantage
May 26, 2009
Engineers Discover Fundamental Flaw In Transistor Noise?
I copy here a part of a post in EDN (follow the link to get the full story... be aware that this seems to be quite yellowish press!!!):
According to the engineers at the National Institute of Standards and Technology (NIST) who discovered the problem, it will soon stand in the way of creating more efficient, lower-powered devices like cell phones and pacemakers unless we solve it.
According to the engineers at the National Institute of Standards and Technology (NIST) who discovered the problem, it will soon stand in the way of creating more efficient, lower-powered devices like cell phones and pacemakers unless we solve it.
While exploring transistor behavior, the team found evidence that a widely accepted model explaining errors caused by electronic "noise" in the switches does not fit the facts. A transistor must be made from highly purified materials to function; defects in these materials, like rocks in a stream, can divert the flow of electricity and cause the device to malfunction. This, in turn, makes it appear to fluctuate erratically between "on" and "off" states. For decades, the engineering community has largely accepted a theoretical model that identifies these defects and helps guide designers' efforts to mitigate them.
Those days are ending, says NIST's Jason Campbell, who has studied the fluctuations between on-off states in progressively smaller transistors. The theory, known as the elastic tunneling model, predicts that as transistors shrink, the fluctuations should correspondingly increase in frequency.
However, Campbell's group at NIST has shown that even in nanometer-sized transistors, the fluctuation frequency remains the same. "This implies that the theory explaining the effect must be wrong," Campbell said. "The model was a good working theory when transistors were large, but our observations clearly indicate that it's incorrect at the smaller nanoscale regimes where industry is headed."
The findings have particular implications for the low-power transistors currently in demand in the latest high-tech consumer technology, such as laptop computers. Low-power transistors are coveted because using them on chips would allow devices to run longer on less power—think cell phones that can run for a week on a single charge or pacemakers that operate for a decade without changing the battery. But Campbell says that the fluctuations his group observed grow even more pronounced as the power decreased. "This is a real bottleneck in our development of transistors for low-power applications," he says. "We have to understand the problem before we can fix it—and troublingly, we don't know what's actually happening."
Campbell, who credits NIST colleague K.P. Cheung for first noticing the possibility of trouble with the theory, presented* some of the group's findings at an industry conference on May 19, 2009, in Austin, Texas. Researchers from the University of Maryland College Park and Rutgers University also contributed to the study.
May 24, 2009
Students from Microelectronics Students’ Group win Cadence® Contest
CADENCE® EMEA (Europe, Middle East and Africa regions) organized the first full custom design contest, entitled Virtuoso Olympics. In this unique and innovative event the best layout designers from the top academic institutions in Europe will compete for the title of Fastest full custom layout designer of the year.
Two students from the Microelectronics Students’ Group of the University of Porto (FEUP) won this Cadence® contest. Daniel Oliveira and Américo Dias accepted the challenge and accomplished the target, wining the first place.
Two students from the Microelectronics Students’ Group of the University of Porto (FEUP) won this Cadence® contest. Daniel Oliveira and Américo Dias accepted the challenge and accomplished the target, wining the first place.
May 22, 2009
An interesting discussion in LinkedIn
There is an interesting thread in LinkedIn, started by Antonio Irvin Aquino:
Is there a market for outsourced device modelling/simulation??
By the moment, I've seen no comments, but I should think that, at least, there is a market for outsourced device models courses...
Is there a market for outsourced device modelling/simulation??
By the moment, I've seen no comments, but I should think that, at least, there is a market for outsourced device models courses...
May 21, 2009
Papers in Solid-State Electronics, May 2009
Three interesting new papers in the May 2009 issue of Solid-State Electronics:A new analytical threshold voltage model for the doped polysilicon thin-film transistors
Weijing Wu, Ruohe Yao, Xueren Zheng
Compact model of short-channel MOSFETs considering quantum mechanical effects
G.S. Jayadeva, Amitava DasGupta
Modeling of kink effect in polycrystalline silicon thin-film transistors
Wanling Deng, Xueren Zheng
May 18, 2009
IEDM'09
The 2009 IEEE International Electron Devices Meeting (IEDM) will be held in the Hilton Baltimore Hotel in Baltimore (MD) from December 6 to 9 2009. This time IEDM will not be held in Washington after the San Francisco edition!
IEDM is the top conference in the field of electron devices. It is of course the most competitive one. Only truly outstanding papers are accepted. It is highly recommended that experimental results are shown, also some good simulation papers can be also accepted.
Two short courses will be held on Sunday, December 6, on on low power/low energy circuits and scaling challenges.
This year there will also be three plenary presentations. Furthermore, there will be a An Emerging Technology session on "Graphene Nanoelectronics".
Deadline for abstract submissions is June 26 2009 at 5.00 pm Pacific Standard Time.
Topics include all aspects related to electron devices, grouped in several areas:
-CMOS DEVICES & TECHNOLOGY (CDT)
-CHARACTERIZATION, RELIABILITY and YIELD (CRY)
-DISPLAYS, SENSORS, AND MEMS (DSM)
-MEMORY TECHNOLOGY (MT)
-MODELING AND SIMULATION (MS)
-PROCESS TECHNOLOGY (PT)
-QUANTUM, POWER, AND COMPOUND SEMICONDUCTOR DEVICES (QPC)
-SOLID STATE AND NANOELECTRONIC DEVICES (SSN)
This year the area of Modeling and Simulation (MS) explicitly includes "physical and compact models for devices and interconnects", and also "parameter extraction", and "early compact models for advanced technologies." It seems that compact modeling is considered a more important topic in IEDM than ever before!
If you have important results to show, I vively recommend to send an abstract to IEDM. It is the best place to present them, and to discuss them with the top people. Even if your abstract is rejected, or if you do not have any new results to show, I encourage researchers to attend IEDM, including compact modeling researchers.
BMAS'09
The 2009 IEEE International Behavioral Modeling and Simulation Conference (BMAS 2008) will be held in San Jose, CA, on September 17-18, in conjunction with the 2009 Custom Integrated Circuits Conference (CICC), in the Doubletree Hotel in San Jose, at the heart of Silicon Valley.
BMAS addresses behavioral modeling and simulation for analog electronic circuits and systems. One of the main areas of topics is "Semiconductor Device Compact Modeling", which includes: " Compact device modeling lanuages and compilers", "Standard and new compact device models implemented in Verilog-A and VHDL-AMS", and "Compact device models for emerging technologies and topical issues (nano-devices, distributed thermal effect, leakaging issues, manufacturability, radiation effects, etc)".
The deadline for paper submission is May 18 2009.
For compact and behavioral modeling researchers, BMAS is no doubt a very interesting conference to attend, and for circuit designers, it is a very good complement to CCIC.
Open Ph D Student position in semiconductor device modeling
We offer one scholarship for a Ph D student position in the Department of Electronic Engineering in the Universitat Rovira i Virgili (URV), in
The duration of the grant will be for four years. The monthly salary will be about 1000 Euro/month. The position will start in January 2009.
The candidate should have a Bachelor or Master degree in Electrical Engineering, Electronic Engineering, Telecommunication Engineering or Physics. A good background in Semiconductor Physics, Semiconductor Devices, or Integrated Circuit Design will be highly appreciated.
The work to be done by the candidate will be focused on the development of new techniques of characterization and modeling of novel advanced semiconductor devices, in particular III-V devices. It will be related to one European projects in which the hosting group participates.
Required documents for applicants
Applicants are required to send to the address specified below the following documents (in English or Spanish):
1) a full Curriculum Vitae (as complete as possible)
2) Copy of their diploma
3) copy of their passport
4) Academic certificate including their marks (it is important that the number of hours or credits of each subject appears). It is also very important that the document specifies what is the minimum mark for passing a given subject and what is the maximum mark that can be awarded.
Candidates can send their documents by e-mail, but in fact we will need original and copy documents (or authenticated copy) of them; therefore we also suggest to send the documents by postal mail.
Applications should be sent to:
Prof. Benjamin Iñiguez
Department of Electronic, Electrical and Automatic Control Engineering
Universitat Rovira i Virgili (URV)
Avinguda Països Catalans, 26
43007
Email: benjamin.iniguez@gmail.com
Tel: +34977558521 Fax:+34977559610
Deadline:
You can contact Prof. Benjamin Iñiguez (Benjamin.Iniguez@gmail.com) for more information
May 12, 2009
Nano-Net 2009: International ICST Conference on Nano-Networks
Fourth International ICST Conference on Nano-Networks
18-20 October, 2009, Lucerne, Switzerland
The Nano-Net 2009 conference positions itself at the intersection of two worlds, namely, emerging nanotechnologies on one side, and Information & Communication Technologies on the other side. One of the standing questions that this conference addresses is: What are the new communication paradigms that derive from the transition from micro- to nano-scale devices? The convergence of nano-technologies with established and novel engineering disciplines such as communication and network theory, sensors and actuators, and biomedical engineering is expected to radically shift our notions about efficient system and network design. Nano- Net provides a unique multidisciplinary forum for the discussion of novel techniques in modeling, design, simulation, and fabrication of nano-scale systems.
The Nano-Net 2009 conference invites original technical papers that have not been published and are not currently under review for publication elsewhere. Contributions addressing subjects pertaining to nanotechnology and networking are solicited. Suggested topics include, but are not limited to the following:
18-20 October, 2009, Lucerne, Switzerland
The Nano-Net 2009 conference positions itself at the intersection of two worlds, namely, emerging nanotechnologies on one side, and Information & Communication Technologies on the other side. One of the standing questions that this conference addresses is: What are the new communication paradigms that derive from the transition from micro- to nano-scale devices? The convergence of nano-technologies with established and novel engineering disciplines such as communication and network theory, sensors and actuators, and biomedical engineering is expected to radically shift our notions about efficient system and network design. Nano- Net provides a unique multidisciplinary forum for the discussion of novel techniques in modeling, design, simulation, and fabrication of nano-scale systems.
The Nano-Net 2009 conference invites original technical papers that have not been published and are not currently under review for publication elsewhere. Contributions addressing subjects pertaining to nanotechnology and networking are solicited. Suggested topics include, but are not limited to the following:
- Emerging nano-devices and fabrication technologies
- Modeling and simulation of nano-devices and systems
- Nano-materials, nano-photonics
- Nano-electronics and architectures
- Reliability and fault-tolerance
- Nano-networks
- Nano-bio paradigms and applications
- Nanosensor Self-Organization
- Nano-mechatronics
- Emerging topics in nano-technologies
Important dates
- Workshop/Tutorial Proposals:May 31, 2009
- Paper Submissions: May 15, 2009
- Acceptance Notification:June 15, 2009
- Camera-Ready Version: July 15, 2009
- Nano-Net 2009 Conference: October 18-20, 2009
May 9, 2009
2009 IEEE International SOI Conference Deadline Extended
SUBMISSION DEADLINE EXTENDED!
The 2009 IEEE International SOI Conference Committee has extended the deadline
for submission of papers to be considered for presentation at the conference to
be held in Silicon Valley, California this October until 29-MAY.
This year's SOI conference will be highlighted by exciting invited talks. Some
of the topics to be covered are Synopsis, Rambus and Freescale on SOI design, on
technology from IBM and IMEC discussing the extendibility of SOI
technology beyond node 22nm to 16nm and 11; Peregrine will discuss RF
applications while Corning will present Silicon on Glass; and Soitec and Leti
will discuss the enabling possibilities of molecular bonding towards 3D
integration and nanotechnology. With the momentum that SOI based technologies is
gaining, the SOI conference is the ideal forum to exchange and network. The SOI
conference is an enriching forum where not only digital and power IC electronics
is discussed but also expands discussion to wafer engineering and circuit
transfer techniques opening up a spectrum of new applications like 3D,
photonics, nano-technologies and devices architectures beyond CMOS.
Submissions should be sent to soipaper@bacminc.com. Further information about
the conference, including an abstract template, can be found on the conference
web site at www.soiconference.org, or you may call the conference manager at
310/305-7885.
The 2009 IEEE International SOI Conference Committee has extended the deadline
for submission of papers to be considered for presentation at the conference to
be held in Silicon Valley, California this October until 29-MAY.
This year's SOI conference will be highlighted by exciting invited talks. Some
of the topics to be covered are Synopsis, Rambus and Freescale on SOI design, on
technology from IBM and IMEC discussing the extendibility of SOI
technology beyond node 22nm to 16nm and 11; Peregrine will discuss RF
applications while Corning will present Silicon on Glass; and Soitec and Leti
will discuss the enabling possibilities of molecular bonding towards 3D
integration and nanotechnology. With the momentum that SOI based technologies is
gaining, the SOI conference is the ideal forum to exchange and network. The SOI
conference is an enriching forum where not only digital and power IC electronics
is discussed but also expands discussion to wafer engineering and circuit
transfer techniques opening up a spectrum of new applications like 3D,
photonics, nano-technologies and devices architectures beyond CMOS.
Submissions should be sent to soipaper@bacminc.com. Further information about
the conference, including an abstract template, can be found on the conference
web site at www.soiconference.org, or you may call the conference manager at
310/305-7885.
May 8, 2009
OSC'09
The 2008 Organic Semiconductor Conference (OSC-09) will take place in London (UK), from September 28 to 30 2009. The conference will be held at the London Heathrow Marriott Hotel. The hotel is conveniently located less than half a mile from Heathrow airport and has excellent road and public transport links to London and the rest of the UK.
OSC-09 includes sessions with presentations by invited speakers plus sessions with peer review papers, a poster session, and also an exhibition of leading organic semiconductor technology companies.
In addition, eight new pre-conference seminars covering a selection of popular topics will be held on Monday 28 September 2009. One seminar stream will be aimed at industry professionals to help them update and extend their knowledge, while a second stream will enable those new to the industry get up to speed. The invited speakers come from both academia and industry.
The Call for Papers will be published very soon. Topics include all aspects related to development, manufacturing and investment in organic semiconductor technologies and organic electronics. Besides, this year the conference will also explore the new opportunities offered by advances in carbon-based electronics.
OSC is not only attended by researchers in organic semiconductors, or organic electronics, but also by chief technology officers, senior technical staff, business leaders, investors, and manufacturers working in this promising field. Therefore, attending OSC there are great opportunities of business in all respects!
OSC-09 includes sessions with presentations by invited speakers plus sessions with peer review papers, a poster session, and also an exhibition of leading organic semiconductor technology companies.
In addition, eight new pre-conference seminars covering a selection of popular topics will be held on Monday 28 September 2009. One seminar stream will be aimed at industry professionals to help them update and extend their knowledge, while a second stream will enable those new to the industry get up to speed. The invited speakers come from both academia and industry.
The Call for Papers will be published very soon. Topics include all aspects related to development, manufacturing and investment in organic semiconductor technologies and organic electronics. Besides, this year the conference will also explore the new opportunities offered by advances in carbon-based electronics.
OSC is not only attended by researchers in organic semiconductors, or organic electronics, but also by chief technology officers, senior technical staff, business leaders, investors, and manufacturers working in this promising field. Therefore, attending OSC there are great opportunities of business in all respects!
TNT'09
The Trends in Nanotechnology conference (TNT 2009) will be held in Barcelona (Catalonia, Spain) on September 7-11 2009.
TNT aims to present a broad range of top research in Nanoscience and Nanotechnology worldwide as well as related policies (European Commission, etc.) and initiatives (iNANO, IEEE, GDR-E, FinNano, etc.). TNT events have shown that they are particularly instrumental to disseminate information and establishing contacts among researchers in this field. Graduate students attending TNT have the chance to learn the importance of interdisciplinary skills, thereby becoming more effective in their future research.
TNT conferences provide an ideal venue for industrial, academic and governmental organizations to discuss common objectives and drive the commercialisation of nanotechnology discoveries.
One of the main goals of the Trends in Nanotechnology conference is to provide a platform where young researchers can present their latest work and also interact with high-level scientists. For this purpose, the Organising Committee provides every year travel grants for students. In addition, more than 20 awards are given to young PhD students for their contributions presented at TNT.
This year, TNT2009 organisation will provide around 100 graduate grants for PhD students:
- 10 Basque Country graduate grants (covering student fee) sponsored by NanoBasque / 325 Euros each - on the basis first come / first served
- 10 European graduate grants (travel bursaries) sponsored by GDR-I (topic of research: Nanotubes & Graphene) / 300 Euros each
- 40 nanoaracat graduate grants sponsored by nanoaracat:
-20 graduate grants for Aragon (travel bursaries) / 250 Euros each
-20 graduate grants for Cataluña (reduced fee) / student fee: 175 Euros (instead of 325)**after notification, a specific registration form will be available online to be able to register with the specific reduced fee.
- 20 Canadian PhD students: 1000 Canadian dollars travel-ship grants
- 20 graduate grants (travel bursaries) sponsored by TNT2009 organisation / 150 Euros each
The TNT2009 Organisation will also provide awards to the best posters presented by students
TNT2009 Deadlines:
Abstract Submission (Oral request): May 11,
2009 Student Grant (Travel bursary) Request: May 11, 2009
Submission (Poster request): July 20, 2009
Weather is usually very nice in Barcelona during the first half of September. Warm enough to go to the nice beaches that are at the city, or close to it, and swim on the sea. And not too hot to walk around.
TNT aims to present a broad range of top research in Nanoscience and Nanotechnology worldwide as well as related policies (European Commission, etc.) and initiatives (iNANO, IEEE, GDR-E, FinNano, etc.). TNT events have shown that they are particularly instrumental to disseminate information and establishing contacts among researchers in this field. Graduate students attending TNT have the chance to learn the importance of interdisciplinary skills, thereby becoming more effective in their future research.
TNT conferences provide an ideal venue for industrial, academic and governmental organizations to discuss common objectives and drive the commercialisation of nanotechnology discoveries.
One of the main goals of the Trends in Nanotechnology conference is to provide a platform where young researchers can present their latest work and also interact with high-level scientists. For this purpose, the Organising Committee provides every year travel grants for students. In addition, more than 20 awards are given to young PhD students for their contributions presented at TNT.
This year, TNT2009 organisation will provide around 100 graduate grants for PhD students:
- 10 Basque Country graduate grants (covering student fee) sponsored by NanoBasque / 325 Euros each - on the basis first come / first served
- 10 European graduate grants (travel bursaries) sponsored by GDR-I (topic of research: Nanotubes & Graphene) / 300 Euros each
- 40 nanoaracat graduate grants sponsored by nanoaracat:
-20 graduate grants for Aragon (travel bursaries) / 250 Euros each
-20 graduate grants for Cataluña (reduced fee) / student fee: 175 Euros (instead of 325)**after notification, a specific registration form will be available online to be able to register with the specific reduced fee.
- 20 Canadian PhD students: 1000 Canadian dollars travel-ship grants
- 20 graduate grants (travel bursaries) sponsored by TNT2009 organisation / 150 Euros each
The TNT2009 Organisation will also provide awards to the best posters presented by students
TNT2009 Deadlines:
Abstract Submission (Oral request): May 11,
2009 Student Grant (Travel bursary) Request: May 11, 2009
Submission (Poster request): July 20, 2009
Weather is usually very nice in Barcelona during the first half of September. Warm enough to go to the nice beaches that are at the city, or close to it, and swim on the sea. And not too hot to walk around.
IEEE SCV EDS upcoming meetings
- EDS Meeting “Power and Variability”- May 12th (Tue)
- Joint EDS-CPMT meeting “Through-Si vias” – May 13th (Wed)
- EDS Meeting “NBTI in PMOS”- June 9th (Tue)
May 7, 2009
ICECS'09, Dec. 13-16 2009, Hammamet, Tunisia
The 16th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2009, will be held in Tunisia on the 13th to 16th December 2009.
The IEEE International Conference on Electronics, Circuits, and Systems (ICECS) is the flagship conference of the IEEE Circuits and Systems (CAS) Society in region 8 (Europe, Middle East and Africa). It presents design methodologies, techniques and experimental results in emerging electronics, circuits and systems topics. ICECS 2009 will include tutorials, regular sessions (lecture and poster), Special sessions and exhibitions.
The IEEE International Conference on Electronics, Circuits, and Systems (ICECS) is the flagship conference of the IEEE Circuits and Systems (CAS) Society in region 8 (Europe, Middle East and Africa). It presents design methodologies, techniques and experimental results in emerging electronics, circuits and systems topics. ICECS 2009 will include tutorials, regular sessions (lecture and poster), Special sessions and exhibitions.
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