[C4P] ESSERC 2026

ESSERC 2026 PAPERS SUBMISSION DEADLINE 

APRIL 3, 2026

Papers submitted for ESSERC 2026 review must clearly state:

• The purpose of the work
• How and to what extent it advances the state-of-the art
• Specific results and their impact.

Only work that has not been previously published or submitted elsewhere will be considered. Submission of a paper for review and subsequent acceptance is considered as a commitment that the work will not be publicly available prior to the conference. Measurement results or calibration against measured data is required to support the claims of the submitted paper.

ESSERC 2026 Conference Tracks 

1. Advanced Technology, Process and Materials
2. Analog, Power and RF Devices
3. Modelling and Simulation of Electron Devices
4. Analog Circuits
5. Data Converters
6. RF & mm‑Wave Circuits
7. Frequency Generation Circuits
8. Digital Circuits & Systems
9. Power Management
10. Wireless Systems
11. Wireline and Optical Circuits and Systems
12. Emerging Computing Devices and Circuits
13. Architectures and Circuits for AI and ML
14. Devices & Circuits for Sensors, Imagers and Displays

After selection of papers, the authors will be informed about the decision of the Technical Program Committee by e-mail by May 27, 2026.

At the same time, the complete program will be published on the conference website. An oral presentation will be given at the Conference for each accepted paper. No-shows will result in the exclusion of the papers from any conference related publication. The submitted final PDF files must be IEEE Xplore compliant.

Best Paper Award: Papers presented at the conference will be considered for the “Best Paper Award” and “Best Young Scientist Paper Award”. The selection will be based on the results of the paper selection process and the judgment of the conference participants. The award delivery will take place during ESSERC 2027.

For each paper independently, at least one (co-)author is required to register for the conference (one registration one paper policy). Registration fees and deadlines will be available on the conference website.

 

[papers] Compact/SPICE Modeling

[1] Kotecha, Ramachandra M., Md Maksudul Hossain, Arman Rashid, Asif Emon, Yuzhi Zhang, and Homer Ei C. Alan Mantooth. "Compact Modeling of High-Voltage Gallium Nitride Power Semiconductor Devices for Advanced Power Electronics Design." IEEE Open Journal of Power Electronics (2021)

Fig: (a) Structure of field-plated GaN transistor (b) Equivalent sub-circuit topology

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[2] Sengupta, Sarmista, and Soumya Pandit. "A Unified Model of Drain Current Local Variability due to Channel Length Fluctuation for an n-Channel EδDC MOS Transistor." (researchsquare.com 2021).

Fig: Schematic diagram of an Epitaxial δ doped n-channel MOS transistor used for design purpose and the graded retrograde approximation of the channel profile of EδDC transistor.

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[3] Patil, C.V., Suma, M.S. Compact modeling of through silicon vias for thermal analysis in 3-D IC structures. Sādhanā 46, 35 (2021). https://doi.org/10.1007/s12046-020-01549-1

Fig: Through Silicon Via 2D representation and its equivalent subcircuit.

[papers] Compact Modeling

Q. C. Nguyen, P. Tounsi, J. Fradin and J. Reynes, "Development of SiC MOSFET Electrical Model and Experimental Validation: Improvement and Reduction of Parameter Number," 2019 MIXDES - 26th International Conference "Mixed Design of Integrated Circuits and Systems", Rzeszów, Poland, 2019, pp. 298-301.

doi: 10.23919/MIXDES.2019.8787050

Abstract: In this work, a new approach for electrical modeling of Silicon Carbide (SiC) MOSFET is presented. The developed model is inspired from the Curtice model which is using a mathematic function reflecting MOSFET output characteristics. The first simulation results showed good agreement with measurements. Improvement is needed in order to increase model accuracy and to take into account the influence of the junction temperature on device characteristics.

D. Kasprowicz, "Semiconductor Device Parameter Extraction Based on I–V Measurements and Simulation," 2019 MIXDES - 26th International Conference "Mixed Design of Integrated Circuits and Systems", Rzeszów, Poland, 2019, pp. 321-326.

doi: 10.23919/MIXDES.2019.8787195

Abstract: The paper presents a method for extracting the physical parameters of a semiconductor device based on the measurements of its electrical response (e.g. transfer characteristics) combined with simulation. Such extraction is usually performed by an optimization algorithm seeking device-parameter values that minimize the difference between the measured response and its simulated equivalent. The proposed approach needs only an average of 13 objective-function evaluations, i.e. device simulations, to extract three parameters of a single device. If the parameters of a group of devices of the same type are to be extracted, the average number of simulations drops to four per device. This number is much smaller than in conventional optimization procedures. Thus, the proposed procedure can be used even in the absence of an accurate compact model, when time-consuming TCAD simulation must be used to determine the device’s response.

D. Tomaszewski, J. Malesińska, G. Głuszko and K. Kucharski, "Current vs Substrate Bias Characteristics of MOSFETs as a Tool for Parameter Extraction," 2019 MIXDES - 26th International Conference "Mixed Design of Integrated Circuits and Systems", Rzeszów, Poland, 2019, pp. 87-91.

doi: 10.23919/MIXDES.2019.8787068

Abstract: An application of the drain current vs substrate bias characteristics of MOSFETs for the device parameter extraction is presented. Modeling of the substrate bias effect on the MOSFET drain current is briefly discussed. A method of the MOSFET characterization is formulated. It requires a measurement of two I(V) characteristics, including the ID(VBS) smooth curve measured in a "sweep" mode. The method allows to extract the threshold voltage parameters and to estimate the in-depth doping profile in the substrate. The proposed approach is demonstrated using I(V) data of the MOSFETs manufactured in ITE in a bulk CMOS process.

A new constituent of electrostatic energy in semiconductors

 A new constituent of electrostatic energy in semiconductors

 An attempt to reformulate electrostatic energy in matter

 

 Jean-Michel Sallese

 Swiss Federal Institute of Technology Lausanne Switzerland 

Received: 30 October 2015

Received in final form: 29 January 2016

Published online: 1 June 2016

Eur. Phys. J. B, 89 6 () 136
DOI: http://dx.doi.org/10.1140/epjb/e2016-60865-4

Abstract: The concept of electric energy is revisited in detail for semiconductors. We come to the conclusion that the main relationship used to calculate the energy related to the penetration of the electric field in semiconductors is missing a fundamental term. For instance, spatial derivate of the electrostatic energy using the traditional formula fails at giving the correct electrostatic force between semiconductor based capacitor plates, and reveals unambiguously the existence of an extra contribution to the standard electrostatic free energy. The additional term is found to be related to the generation of space charge regions which are predicted when combining electrostatics with semiconductor physics laws, such as for accumulation and inversion layers. On the contrary, no such energy is needed when relying on electrostatics only, as for instance when adopting the so-called full depletion approximation. The same holds for neutral and charged insulators that are still consistent with the customary definition, but these two examples are in fact singular cases. In semiconductors for instance, this additional energy can largely exceed the energy gained by the dipoles, thus becoming the dominant term. This unexpected result clearly asks for a generalization of electrostatic energy in matter in order to reconcile basic concepts of electrostatic energy in the framework of classical physics.

Keywords: Solid State and Materials

© The Author(s) 2016. This article is published with open access at Springerlink.com

Papers in Solid-State Electronics, May 2009

Three interesting new papers in the May 2009 issue of Solid-State Electronics:

A new analytical threshold voltage model for the doped polysilicon thin-film transistors
Weijing Wu, Ruohe Yao, Xueren Zheng

Compact model of short-channel MOSFETs considering quantum mechanical effects
G.S. Jayadeva, Amitava DasGupta

Modeling of kink effect in polycrystalline silicon thin-film transistors
Wanling Deng, Xueren Zheng