Researchers have an array of new technologies in the pipeline to boost CMOS logic and memory performance, Sematech Vice President Raj Jammy said Tuesday at the Device Scaling TechXPOT at SEMICON West. High-mobility graphene channels, gates built around nanowires, finFETs with III-V materials -- all promise to blow past the power/performance capabilities of silicon CMOS.
David Lammers, News Editor -- Semiconductor International, 7/15/2009
Researchers have an array of new technologies in the pipeline to boost CMOS logic and memory performance, Sematech Vice President Raj Jammy said Tuesday at the Device Scaling TechXPOT at SEMICON West.
| "We need disruptive materials and technologies," said Raj Jammy of Sematech.|
High-mobility graphene channels, gates built around nanowires, finFETs with III-V materials -- all promise to blow past the power/performance capabilities of silicon CMOS. Jammy, in charge of materials and emerging technologies research at Sematech, warned that "people entrenched in the silicon world" may need to rethink as scaling of today's CMOS transistors becomes increasingly difficult.
"We need disruptive materials and technologies," Jammy said, describing R&D progress on several post-22 nm options. Progress is being made on heterogeneous devices, where germanium is used as the channel in the pFET and indium gallium arsenide (InGaAs), for example, on the nFET. Nanowires with a gate-all-around design are drawing more R&D attention, and work continues on finFETs -- vertical structures that allow better control of the channel.
Memory R&D is equally vibrant. For decades, mainstream memories have been based on charge storage. "But when you make these devices really small, charge storage is no longer possible." On the horizon are phase change memories (PCRAMs) and metallic resistive RAMs (ReRAMs), though Jammy acknowledged that the question regarding ReRAM technology is: "Does it work at less than 20 nm?"
Also under study are zero-leakage nanoelectrical-mechanical system (NEMS) devices, which Jammy said "exhibit instant on and off." And because they are mechanical, they can safely operate in hazardous environments, such as a nuclear power plant.
| Schubert Chu of Applied Materials spoke of the potential of carbon-doped silicon for nFET strain.|
Schubert Chu, an Applied Materials product manager for epi/LPCVD products, examined the possibility of embedded silicon carbon (eSiC) being used to enhance the performance of the nFET. While embedded silicon germanium (eSiGe) has served to effectively strain the pFET, SiC has been a tougher challenge, largely because the carbon atoms tend to move around.
Chu said that an AMD-led team has shown a 30% improvement with nFETs strained by SiC structures. "Silicon carbon is on track to be adopted at the 22 nm generation."
SiGe stressors face challenges as the germanium content moves from 25-30% at the 45 nm node to >40% at the 22 nm node. Applied Materials has developed a "Siconi" pre-clean option for its Centura epitaxial deposition tool, which Chu said will extend epi strain technologies.Jammy said the industry faces serious cost challenges. "When we hear that it may cost $80M for a EUV scanner, we are not going in the right direction on costs," he said.