[paper] GaN HEMT Biosensor

Ashkhen Yesayan and Jean-Michel Sallese

Modeling and Sensitivity Analysis of GaN HEMT Biosensor

Biosensors: Section Biosensor and Bioelectronic Devices (2026), 16(9), 520

DOI: 10.3390/bios16090520 

* STI-EDLab, EPFL, Lausanne (CH)

Abstract: Gallium nitride (GaN) high-electron-mobility transistor (HEMT) biosensors have recently emerged as promising platforms for highly sensitive and label-free detection of biomolecules. Their exceptional electrical properties, including high carrier mobility, together with the wide bandgap and strong chemical bonds of GaN materials, provide excellent stability under high temperatures, ionizing radiation, and chemically harsh environments. Despite significant experimental progress, comprehensive analytical models capable of linking biomolecular recognition events to the electrical response of GaN biosensors remain limited. This work presents a physics-based, design-oriented analytical modeling framework for AlGaN/GaN HEMT biosensors. The model incorporates biomolecular binding kinetics, the dielectric properties of the hybrid system, and electrostatic coupling to the transistor channel conductivity. Numerical simulations are performed using commercial multiphysics software to validate the analytical model. The developed framework provides physical insight into the mechanisms governing biosensor operation and offers practical guidelines for the optimization and comparative assessment of HEMT/MIS-HEMT biosensor architectures.

FIG: Typical GaN HEMT structure with a simplified representation of the functionalization and diffuse layers (not to scale) and corresponding IV plot at different gating potentials induced by analyte concentration variations, obtained from the analytical model and numerical simulations.

Acknowledgments: This work was funded by the SNSF Foundation project 200021 213116. During the preparation of this manuscript the authors used GPT-5.6 Luna to draw the picture in Figure 1. The authors have reviewed and edited the output and take full responsibility for the content.

[FOSS] AI IC Designs

Harald Pretl, Kevin Cameron, Jun‑ichi Okamura

FOSS AI IC Designs Examples

Intensive work over last three months was carried out by Prof. Harald Pretl together with an AI coding agent, thru which a substantial chip‑design knowledge base was built. At this stage, the AI agent is able to design, simulate, and layout a low‑noise, low‑voltage bandgap reference plus LDO with minimal manual intervention (along with many additional circuits that will be showcased later). The rapid progress in capability development is highly impressive.

The entire implementation was performed in OpenPDK 130nm CMOS using IIC‑OSIC‑TOOLS with almost no human involvement. The resulting layout is densely packed, the floorplan is coherent, and a manually created version would not differ significantly. Dummy structures were inserted for matching, and common‑centroid placement was applied to critical MOSFET devices.

Significant progress has also been achieved by Kevin Cameron, primarily on the simulation side, covering complete digital and AMS/RF domains. The work described in the linked repository has been developed and advanced accordingly, with sv2ghdl, which translates SystemVerilog RTL into VHDL for use with GHDL and NVC simulators. The generated VHDL leverages simulator extensions that go beyond what SystemVerilog offers, including multi‑UDN wires, bidirectional components, and improved unknown‑state handling

<https://github.com/kev-cam/sv2ghdl/blob/main/README.md>

A beta version of an automatic P&R tool for the OpenPDK TR‑1um was developed by Jun‑ichi Okamura using Claude AI and FOSS KLayout API and accompanying verification scripts. The flow is based on the newly updated standard‑cell library, incorporating both LEF and Liberty files, and STA analysis is now supported. Regression testing was carried out on three designs: I²C, SPI, and TD4

<https://lnkd.in/gMy3ThYm>

The synthesis and automatic P&R of TD4, an educational 4‑bit CPU, were completed by Jun‑ichi Okamura using Claude AI and the OpenPDK TR‑1um flow. A custom 8×16 register file was designed, the standard‑cell height was reduced, and a simplified Liberty (.lib) file was created to enable static timing analysis. The final chip implementation is made up of 4225 devices.

[githib] Teaching Analog Electronics in Minecraft

Rodrigo Picos, Stavros G. Stavrinides, George Stavrinides, Ariadna Picos, and Gerard Picos.

CircuitSimCraft: a Fabric mod for teaching analog electronics in Minecraft

https://github.com/rpicos-uib/circuitsimcraft (2026)

CircuitSimCraft: a Fabric mod that turns Minecraft into an analog electronics lab. Place resistors, capacitors, inductors and memristors as blocks, wire them up, drive them with power supplies and function generators, and probe the live voltage/current with a handheld oscilloscope — all backed by a real modified-nodal-analysis (MNA) circuit solver, the same family of algorithm SPICE uses, not a scripted approximation.

This is a teaching tool: the goal is for the in-game behavior to actually match what you'd see on a real bench (RC charge curves, RL transients, a memristor's resistance drifting with accumulated charge), just at Minecraft-tick timescales instead of real-world ones.

[paper] 12nm FinFETs from 292K to 10mK

D. Lee, J. Lee, L. Jin, R. Rangaraj, L. Shao and J. S. Walling

12nm FinFETs from 292K to 10mK:

Characterization and a Temperature-Continuous Compact Model for Qubit Control

Preprint arXiv:2609.11963 (19 Aug 2026)

1 Bradley Department of Electrical and Computer Engineering, Virginia Tech, Blacksburg, VA, USA

Abstract: We report cryogenic characterization and compact modeling of GlobalFoundries (GF) 12LP regular-voltagethreshold (RVT) n- and p-FinFETs, measured from 292K to 10mK. Both devices retain sub-Kelvin gate control without carrier freeze-out, with the n-type device exhibiting an intrinsic subthreshold slope (SS) floor of 24.8 mV/dec. To bypass high on-chip series routing resistance that confounds peak-gm extraction, we adopt a fixed-current (3.26 μA/μm) methodology. These low current metrics inform a continuous 1.36K to 292K compact model using dynamic parameter injection, preserving room temperature process development kit (PDK) qualification.

Fig: Measured transfer characteristics at |VDS,ext| = 0.8V, shaded dark to light with increasing temperature. Drain current is normalized to gate width, so the dotted line marks the constant-current threshold criterion at ICC = 1μA/μm.

Acknowledgment: The 12nm finFET IC fabrication was provided by GlobalFoundries as part of their University Partnership Program.

[conf] International Conference on Microelectronics

ICM 2026 International Conference on Microelectronics

<https://www.ieee-icm.org/>

7-10 December 2026

Borneo Cultures Museum, Sarawak, Malaysia

The IEEE International Conference on Microelectronics has already been held numerous times in different countries across the MiddleEast, North Africa, and Asia for the past 37 years.

The 38th edition of the conference will take place in Borneo Cultures Museum Sarawak, Malaysia. IEEE-ICM 2026 will include oral, poster sessions and tutorials given by experts on state-of-the-art topics. The regular technical program will run for three days. In addition, tutorial sessions will be held on the first day of the conference.

The theme of ICM 2026, “Innovations in Circuits and Systems for a Sustainable Future,” has been selected in recognition of the unprecedented global challenges related to climate change, healthcare, and energy. Continued innovation and the development of new technological solutions are considered essential for building a more sustainable future. The conference is intended to provide a unique platform for the exchange of ideas and the exploration of new avenues for research and collaboration that may contribute to this objective.

Sincere appreciation is expressed to the keynote speakers, session chairs, reviewers, and volunteers, whose dedicated efforts have contributed significantly to the organization and success of the conference. Gratitude is also extended to the sponsors and exhibitors for their generous support, which has made the event possible.

It is hoped that the conference will be both informative and enjoyable, offering numerous opportunities for networking, learning, and collaboration. On behalf of the organizing committee, best wishes are conveyed for a productive and rewarding experience at ICM 2026.

[read more...]

[webinar] SPICE Device Modeling and Circuit Simulation

Mansun Chan

Circuit Simulation and Device Modeling: From SPICE Fundamentals to Industrial BSIM Models

DOI 10.17023/9439-t168

This tutorial introduces the fundamentals of circuit simulation and compact device modelling for integrated circuit design. Starting from SPICE-based circuit simulation #it explains the role of device models #the requirements for DC #transient #and AC analyses #and the trade-offs between physical accuracy and simulation efficiency. The development of industrial compact models is illustrated using BSIM3 as an example #providing insight into how practical device models are constructed and used in modern circuit design [EDS Education Committee]

More EDS Education Resources like this:

SPICE Models: Problems and Opportunities

Compact Modeling of MOSFETs: Overview and Challenges

#simulation #modeling #circuit #SPICE #bsim #mosfet #transistor #compact #tcad #jacobian #conductance #voltage

[webinar] Silicon for AI

Silicon for AI: Breaking Barriers in IC Fabrication through Open Silicon

[IEEE CAS Webinar]

Join us for a CASS-supported webinar exploring Integrated-Circuit Fabrication through the IEEE DI Open Silicon Initiative

Date: 21 September 2026 at 10:00 AM ET | 7:00 AM PT

Don't miss this opportunity to learn more about efforts to break down barriers to silicon access and support innovation in integrated-circuit design and fabrication.

Register online or using the QR code in the graphic!

#IEEE #IEEECASS #OpenSilicon #IntegratedCircuits #ICDesign #Semiconductors #Silicon #AI

[mos-ak] //ICMC 2027// Conference committees: Call for Participation

Join the ICMC 2027 Organizing Team! The International Compact Modeling Conference 2026 was a great success. ICMC focuses uniquely on compact device models, their development and broad application in the semiconductor industry. We’re excited to announce that preparations are already underway for the next edition on July 15–16, 2027 in San Jose, California. For ICMC information and Photo Gallery, go to https://si2-icmc.org. We are currently seeking enthusiastic volunteers to join the ICMC 2027 conference committees. If you're interested in helping shape next year’s event, please complete this interest survey: https://survey.zohopublic.com/zs/edC25U Summary of Committee Responsibilities: Organizing Committee: Oversees the overall planning and execution of the yearly edition of the ICMC Conference. Coordinates among sub-committees and maintains regular communication to track progress and confirm major decisions. Technical Program Committee: Defines the major topics and focus areas and develops the technical program for the conference, creates the call for papers, and defines, organizes and oversees the paper review procedures. Publicity Committee: Develops and implements the marketing plan to promote the conference and increase its visibility.

About Si2 The Silicon Integration Initiative Inc. is a global, not-for-profit membership organization with approximately 70 corporate members who collaborate on trusted standards and shared solutions that reduce development costs and increase design productivity for semiconductor foundries, fabless design companies, and EDA software providers. Learn more at https://si2.org/.

[conference] IRPhE' 2026 Sept. 28-30 2026, Yerevan

International Conference on Microwave & THz Technologies, Wireless Communications
and OptoElectronics

IRPhE' 2026 

<http://www.irphe.am/?q=conference>  

September 28-30 2026, Yerevan (Armenia)

The upcoming IRPhE' 2026 Conferences is dedicated to 90-years jubilee of academician Radik Martirosyan

IRPhE’ 2026 Main R&D Topics:

• Microwave devices, antennas, propagations and remote sensing
• THz technique, spectroscopy and applications
• Microwave Photonics
• Wireless communications and related information technologies
• Alternative semiconductor and dielectric materials, electronic and optoelectronic devices

Submission Information:

• Original one page abstracts will be accepted for review in Word and PDF formats
• Abstract submission deadline: August 31, 2026
• The authors of accepted abstracts will be invited to submit 4-6 page papers for publication in the Conference Proceedings. Final full paper submission deadline: October 10, 2026
• Best papers selected through peer-review process will be invited for publication in the special issue of a Scopus indexed journal publishing interdisciplinary research between electronics and systems, high speed technology, photonics and electronics (IET Digital Library and IEEE Xplore). Abstracts and papers must be submitted via email: irphe2024@gmail.com

Registration Information:

• For each paper independently, at least one co-author is required to register for the conference
• Registration deadline: September 15, 2026
• In-person registration fee - 200 USD
• virtual registration fee - 100 USD
• registration fee for local participants - 10000 AMD

Organized by:

Higher Education and Science Committee

National Academy of Sciences

Yerevan State University

[EDS Webinar] Emerging Technologies at ESREF 2026

Discover Emerging Tech Trends

IEEE EDS Webinar Series Emerging Technologies at ESREF 2026 Sponsored By: The IEEE Electron Devices Society Educational Activities Committee and Device Reliability Physics Committee The EDS Webinar on Emerging Technologies, held within ESREF 2026 at TU Wien in Vienna, will address recent developments and reliability challenges in emerging device technologies. Topics include 2D FETs, advanced MOS gate stacks, emerging and resistive-switching memories, and memristive devices for neuromorphic computing, covering aspects from device-level reliability and defect engineering to CMOS integration and system-level considerations. Date: 21 September 2026  Time: 9:30 AM - 12:20 PM EDT / 3:30 - 6:20 PM CEST (Time Zone Conversion Tool) Presenters: Dr. Erika Covi, Dr. Saptarshi Das, Dr. Jacopo Franco, Dr. Cristian Zambelli, Dr. Lambert Alff More Information Here This message is being sent on behalf of the EDS Vice President of Educational Activities, P Susthitha Menon As part of our commitment to advancing the vision and mission of the Electron Devices Society, we are pleased to invite you to attend our next scheduled webinar. All participants will receive virtual meeting details prior to the event. We sincerely hope that you can join us for this event. Register to Join Virtually

[map] Poland: Emerging Semiconductor Hub

[Map photo] Karolina Falkenberg | Business Development Expert | Lodz Special Economic Zone

Mas illustrating Poland’s semiconductor ecosystem was presented at SEMICON Taiwan 2026 in Taipei. The Polish national stand was officially opened by Michał Jaros, Secretary of State at the Ministry of Development and Technology. The Lodz Special Economic Zone was represented together with Jacek Podgórski and Janusz Woźny from the Lodz University of Technology, highlighting the investment and research potential of Lodz and Central Poland.

[paper] a-IGZO Thin-Film Transistor Compact Model

Seunghyun Son, Taejun Ha, Taeyoung Nam, Yoonyoung Chung, Sunmean Kim

Bayesian Optimization–Reinforcement Learning Hybrid Framework for a-IGZO Thin-Film Transistor Compact Model Parameter Extraction in 2T0C Dynamic Random Access Memory Applications

Advanced Intelligent Systems (2026): e70525

1.) School of Electronic and Electrical Engineering, Kyungpook National University, Daegu, Republic of Korea

2.) Department of Electrical Engineering, POSTECH, Pohang, Republic of Korea

Abstract: In this work, we propose a two-stage BO–RL hybrid framework for compact model parameter extraction of a-IGZO TFTs. The strategy combines the complementary strengths of Bayesian optimization (BO) and reinforcement learning (RL): BO performs global exploration and provides an optimized starting point, and RL conducts local refinement within a reduced search domain. Experimental results demonstrate that the hybrid method substantially improves extraction efficiency while maintaining fitting accuracy statistically comparable to that of BO or RL alone. Across five independent random seeds under an equal 4000-simulation budget, the fitting quality of BO–RL is statistically comparable to that of BO, while RL alone remains an order of magnitude less sample-efficient; the RL refinement stage requires no surrogate refitting, so its per-simulation cost remains low and constant, and the framework attains comparable fitting quality without the growing optimization overhead of BO. We validate the framework using an a-IGZO TFT compact model, showing good agreement between SPICE-simulated and measured C–V/I–V curves with the extracted parameters. Circuit-level transient simulations of an a-IGZO 2T0C cell demonstrate write/hold operations with a retention time of 172 s.

FIG: Schematic of a-IGZO TFT structure and fabrication process;

SPICE (lines) simulation and experimental data (points) comparison

Acknowledgments: This paper was a result of the research project supported by SK Hynix Inc.

Funding MDUO004A