Showing posts with label International. Show all posts
Showing posts with label International. Show all posts

Dec 26, 2024

[C4P] ICMC 2025

STRENGTHENING MODELING COLLABORATION WITH THE SEMICONDUCTOR INDUSTRY
International Compact Modeling Conference (ICMC 2025)
June 26-27, 2025; The Clift Royal Sonesta, San Francisco

IMPORTANT DATES

Abstract Submission Deadline
January 15, 2025

Acceptance Notifications
March 10, 2025

Full Paper Submission Deadline
April 20, 2025

ORGANIZING COMMITTEE

General Chair
Peter M. Lee Micron 

Vice Chair
Shahed Reza Sandia Lab

Technical Program Chair
Colin Shaw Silvaco

Technical Program Vice Chair
Gert-Jan Smit NXP 

Treasurer
Leigh Anne Clevenger Si2

Secretariat Conference Catalysts
icmc@conferencecatalysts.com








The Compact Model Coalition (CMC) brings academia and industry partners together in the development and standardization of compact models for semiconductor devices. For 30 years now, the CMC has been instrumental in creating standardized and verified models for designers to use in their increasingly complex circuits for SPICE simulation. The CMC is organizing a new and innovative International Compact Modeling Conference. Cosponsored by IEEE EDS, it will focus uniquely on compact device models, their development and broad application in the semiconductor industry. You are invited to participate in the evolution of these models, guide model development to help circuit designers create the best circuit performance possible, and enable foundries to leverage the strength of their device fabrication to full extent. Join the world experts in design, process technology, and model development to discuss state-of-the-art semiconductor device modeling for a two-day in-person event in one location, offering a great opportunity to present and learn about this core element of circuit design and how to get the most from these global collaborations. We are seeking papers for oral or poster presentations in the following areas:

APPLICATION OF DEVICE MODELS
  • Innovative application of CMC standard device models
  • Best practices, novel use, and benefits of standard device models in circuit design
  • Use of compact models to demonstrate foundry device capabilities
DEVICE MODEL DEVELOPMENT
  • Modeling of physical phenomena: Statistical variation, reliability and aging, noise and fluctuations, high frequency effects, Electrostatic Discharge (ESD), self heating, layout effects, etc.
  • Methodologies to assist in model development, practices for coding, quality assurance, circuit simulator integration, etc.
  • Parameter extraction, measurement techniques, model calibration, validation, and verification methodologies, including solutions based on AI or Machine Learning.
MODEL ENHANCEMENTS AND IMPLEMENTATIONS
  • Model extensions to capture additional device features (leakage, noise, capacitance, second-order dependencies, …) or expand the operating range of existing devices (bias, power, temperature, frequency, etc.)
  • Model enhancements to support the design of new or demanding circuits
  • Model workflow, implementation, and integration into the design environment (PDK)
  • Computing/simulation platforms, simulation algorithms, and methodologies to improve simulation performance (parallel processing, etc.)
  • Models for established device types that currently lack standardization.
MODELING FOR FUTURE/EMERGING TECHNOLOGIES AND APPLICATIONS
  • Models for emerging device types or architectures on the horizon, such as, ferroelectric devices, silicon photonics, cryogenic, quantum computing, etc.
  • Modeling of new physical phenomena in support of current and novel device technologies
  • Novel device technologies currently being researched that could further revolutionize circuit performance, have implications in the design flow, and may become mainstream in the future
Please submit your paper proposals in the form of a 2-page abstract for review by January 15, 2025 here 2025.si2-icmc.org. Acceptance notifications will be sent by March 10, 2025. Accepted contributions (for both oral and poster presentations) are expected to submit a camera-ready 4-page draft version of their papers by April 20, 2025 and final version by May 23, 2025 for publication in IEEE Xplore®.

Sep 8, 2023

[conference] 10th Micro Nano 2023

10th International Conference "Micro Nano 2023"
Location: Demokritos Congress Center
Dates: November 2nd-5th 2023

The Micro Nano 2023 Organizing Committee is looking forward to welcoming you to Athens to the 10th International Conference on Micro-Nanoelectronics, Micro-Nanosciences and Nanotechnologies (https://2023.micro-nano.gr), our annual event that brings together Academia, Research and Industry to discuss the latest advancements of the field.

We are happy to announce that the abstract submission is already open and would like to prompt you to submit your work by September 18th. Also, take advantage of the early bird registration discounts, which are open until October the 9th

Visit https://2023.micro-nano.gr/call-for-paper/ to submit your abstract 
and https://2023.micro-nano.gr/fees-registration/ for registration details.

We would like to remind you that this year’s conference includes a Celebratory Special Event for the conference’s 10th Anniversary, scheduled as an Opening Ceremony on the first day (November 2nd, 2023) to commemorate and celebrate 40 years of Microelectronics in Greece. We are also excited about this year’s 
Check our website for more information on the stimulating presentations that lie ahead.

Dates to remember:
  • Abstract submission deadline: September 18th, 2023
  • Early-bird registration: October 9th, 2023
  • Late poster presentation: October 23rd, 2023
Venue:
  • Special Event: Main Hall of the National and Kapodistrian University of Athens (Panepistimiou 30)
  • Special Event (Nov.2): “40 years of Microelectronics in Greece”
    https://2023.micro-nano.gr/special-event/
Technical Program
We are looking forward to seeing you all in November!

On behalf of the Organizing Committee,
Prof. Margarita Chatzichristidi, Conference Chair
Dr. Eleni Makarona, Conference Co-chair

Conference e-mail address: MicroNano2023@chem.uoa.gr


 

Sep 4, 2023

[Proceedings] MNDCS 2023

Micro and Nanoelectronics Devices, Circuits and Systems
Select Proceedings of MNDCS 2023

Part of the book series: Lecture Notes in Electrical Engineering (LNEE, volume 1067) DOI: 10.1007/978-981-99-4495-8

Editors: Trupti Ranjan Lenka, Samar K. Saha, Lan Fu

This book presents select proceedings of the International Conference on Micro and Nanoelectronics Devices, Circuits and Systems (MNDCS-2023). The book includes cutting-edge research papers in the emerging fields of micro and nanoelectronics devices, circuits, and systems from experts working in these fields over the last decade. The book is a unique collection of chapters from different areas with a common theme and is immensely useful to academic researchers and practitioners in the industry who work in this field.


Dec 21, 2018

[mos-ak] [press note] 11th International MOS-AK Workshop, Silicon Valley, December 5, 2018

Modeling of Systems and Parameter Extraction Working Group
11th International MOS-AK Workshop
Silvaco Inc. Headquarters, Silicon Valley, December 5, 2018
Summary

The MOS-AK Compact Modeling Association, a global standardization forum for semiconductor device models, held its 11th MOS-AK Workshop at the Silvaco Inc. headquarters in Santa Clara, Calif. on December 5, 2018. The event was co-located with the 2018 IEEE International Electron Devices (IEDM) and the Q4 Compact Modeling Coalition (CMC) meetings. The workshop receives technical program co-sponsorship from the IEEE Santa Clara Valley-San Francisco Chapter of the Electron Devices Society, Europractice, IJHSES as well as NEEDS of nanoHUB.org.

Bogdan Tudor, Silvaco Inc. and Wladek Grabinski, MOS-AK, welcomed more than 30 international academic researchers and modeling engineers. The nine technical compact modeling presentations covered nanoscale technologies, semiconductor devices modeling and advanced IC design.

The MOS-AK speakers shared their latest perspectives on compact/SPICE modeling and Verilog-A standardization in response to the dynamically evolving semiconductor industry and academic R&D efforts. The event featured advanced technical presentations covering compact model development, implementation, and deployment. For more information about each of the presentations, including full abstracts, go online to MOS-AK Workshop Silicon Valley 2018.

The nine topics presented were the following:
  1. Silvaco GaN HEMT Compact Modeling Perspective, Bogdan Tudor, Colin Shaw and Sungwon Kong, Silvaco, Inc.
  2. GaN HEMT Devices and Modeling for Operational Electronics at Harsh Environments, Saleh Kargarrazi, XLab, Stanford University
  3. Impact of Basal Plane Dislocations and Ruggedness of 10 kV 4H-SiC Transistors, Victor Veliadis, PowerAmerica, North Carolina State University
  4. Direct measurement of white noise in MOSFETs, Kenji Ohmori, Device Lab Inc.
  5. NEREID Technology Roadmap, Enrico Sangiorgi, NEREID, University of Bologna
  6. A Physics-Based Compact Model of RRAM for Emerging Applications, Paolo Pavan, University of Modena and Reggio Emilia
  7. From Physics to Power, Performance, and Parasitics, Oskar Baumgartner, Global TCAD Solutions GmbH
  8. MOS-AK FOSS Compact Modeling Perspective, Wladek Grabinski, IEEE EDS DL, MOS-AK
  9. Compact Model of Single TeraFET Spectrometer, Michael Shur, Rensselaer Polytechnic Institute
There were also presentations of Late News with the following topics:
  1. CMC Developer Model Software Licenses, Peter Lee, Micron
  2. Xyce Parallel Electronic Simulator (Ver. 6.10), Jason Verley, Sandia National Laboratories
  3. Call for Papers for ESSDERC/ESSCIRC 2019 in Krakow, Wladek Grabinski, MOS-AK
Photo: Some of the participants of the 11th MOS-AK Workshop at Silvaco Inc. Headquarters in Silicon Valley.

The MOS-AK Association plans to continue its standardization efforts by organizing future compact modeling meetings, workshops and courses in India, China, Europe, USA and, for the very first time, in Latin America, throughout the coming year, including:
About Silvaco:
Silvaco, Inc. is a leading EDA tools and semiconductor IP provider used for process and device development for advanced semiconductors, power IC, display and memory design. For over 30 years, Silvaco has enabled its customers to develop next generation semiconductor products in the shortest time with reduced cost. We are a technology company outpacing the EDA industry by delivering innovative smart silicon solutions to meet the world's ever-growing demand for mobile intelligent computing. The company is headquartered in Santa Clara, California and has a global presence with offices located in North America, Europe, Japan and Asia.

About Europractice IC Service:
The EUROPRACTICE IC Service brings ASIC design and manufacturing capability within the technical and financial reach of any company that wishes to use ASICs. The EUROPRACTICE IC Service, offered by IMEC and Fraunhofer, offers low-cost ASIC prototyping and ASIC small volume production ramp-up to high volume production through Multi Project Wafer - MPW - and dedicated wafer runs.

About MOS-AK Association:
MOS-AK is an international compact modeling association primarily focused in Europe, to enable international compact modeling R&D exchange in the North/Latin Americas, EMEA and Asia/Pacific Regions. The MOS-AK Modeling Working Group plays a central role in developing a common information exchange system among foundries, CAD vendors, IC designers and model developers by contributing and promoting different elements of compact/SPICE modeling and its Verilog-A standardization and related CAD/EDA tools including FOSS for compact/SPICE model development, validation/implementation and distribution. For more information please visit mos-ak.org