[Open PDK] IEEE EDS DL at IISc Banglare

IEEE EDS/SSCS Bangalore Chapter Presents DL Series

FOSS TCAD/EDA Tools SPICE and Verilog-A

Modeling Flow Technology - Devices - Applications

W.Grabinski, MOS-AK (EU)

DATE AND TIME	LOCATION	HOSTS
Date: 07 Mar 2024 Time: 04:00 PM to 05:00 PM All times are (UTC+05:30) Chennai Add Event to Calendar iCal Google Calendar	Auditorium, Dept. of ESE, IISc Bangalore Karnataka India 560012	Bangalore Section Jt. Chapter ED15/SSC37

Guardian of Verilog-A Compact Models

on 02/02/2020, Geoffrey Coram, Staff CAD Engineer at Analog Devices and Verilog-A Recommended Practices CMC Chair was honored by Prof. Chenming Hu and the BSIM Group at UC Berkeley, naming him as "Guardian of Verilog-A Compact Models for the Global Semiconductor Industry"

[paper] Benchmark Tests for MOSFET Thermal Noise Models

Scholten A.J., Smit G.D.J., Pijper R.M.T., Tiemeijer L.F.

Benchmark Tests for MOSFET Thermal Noise Models

In: Grasser T. (eds) Noise in Nanoscale Semiconductor Devices. Springer, Cham

Abstract - In today’s semiconductor industry, many traditional integrated device manufacturers (IDMs) are moving away from chip manufacturing, and transforming into fabless companies that use foundry services for manufacturing their ICs. This is especially true in the field of advanced CMOS technologies. In these companies-under-transformation, the work of the modeling engineer is changing: instead of building models from scratch themselves, most companies choose to use the modeling packages that are delivered by the foundries. There are two reasons to be skeptical about RF noise models. First, measurement of noise, and RF noise in particular, is a difficult and specialist topic. One should not take for granted that every company has the required expertise to carry out this task successfully. A second reason to check RF noise models is that the most popular compact MOSFET models are BSIM4 [1] and BSIMBULK [2], which are not particularly strong and certainly not predictive when it comes to RF noise. As a consequence, the work of the modeling engineer is changing from model creation to model verification.

Tab: Overview of benchmark tests for thermal noise

#No	Bias	Length	Quantity	Test	Remark
#1	VDS = 0V	All	SID	γ = 1
#2	VDS = 0 V	All	SIG	β = 5/12
#3	VDS = 0 V	All	c	c = 0	In the limit f ↓ 0 Hz
#4	Weak Inv	All	SID	F = 1	Disregard SIG contributions from gate to drain
#5	Saturation	Long	SID	γ = 2/3
#6	Saturation	Long	SIG	β = 4/3
#7	Saturation	Long	c	c = 0.4j
#8	Saturation	Short	SID	γ enhancement	Switch off gate resistance
#9	Saturation	All	SID	γ D,NMOS ≥ γ D,PMOS	Switch off gate resistance
#10	Saturation	All	SID	Different Vth flavors should nearly coincide	When plotted against ID

First Online: 27 April 2020

DOI: 10.1007/978-3-030-37500-3_20

Ref: 

[1] N. Paydavosi, T.H. Morshed, D.D. Lu, W. Yang, M.V. Dunga, X. Xi, J. He, W. Liu, K.M. Cao, X. Jin, J.J. Ou, M. Chan, A.M. Niknejad, C. Hu, BSIM4v4.8.0 MOSFET Model - User’s Manual. [Online]. Available: http://bsim.berkeley.edu/models/bsim4/

[2] H. Agarwal, C. Gupta, H.-L. Chang, S. Khandelwal, J.P. Duarte, Y.S. Chauhan, S. Salahuddin, C. Hu, BSIM-BULK106.2.0 MOSFET Compact Model - Technical Manual. [Online]. Available: http://bsim.berkeley.edu/models/bsimbulk/

4th Training Course on Compact Modeling

 4th Training Course on Compact Modeling 

 (TCCM) 

 in Tarragona on June 27-28 2016

The 4th TCCM is partially sponsored by the DOMINO H2020 project. It will consist a series of lectures conducted by prestigious researchers in the field of modeling of semiconductor devices, dealing with several issues related to the semiconductor device modeling, mostly compact/SPICE modeling. It is a very interesting event to PhD students and young researchers, but can interest senior researchers too.

Invited TCCM Lecturers:

• Morgan Madec (Univ of Strasbourg, France): Compact modeling for biological applications
• Mansun Chan (Hong Kong University of Science and Technology): An Integrated Approach for Circuit Performance and Reliability Simulation
• Mohammed Nawaz (ABB Sweden): Static and dynamic characterization of SiC based MOSFETs/IGBTs
• Christoph Jungemann (RWTH-Aachen): TCAD and semiclassical device modeling
• Antonio Cerdeira (CINVESTAV, Mexico): Model parameter extraction techniques
• Fabrizio Torricelli (Univ. of Brescia, Italy): Modelling of Amorphous-Oxide-Semiconductors TFTs for large-area flexible electronics
• Eugenio Cantatore (TU-Eindhoven): Application of compact models for organic circuit design
• Ahmed Nejim (Silvaco): TCAD for compact model development
• Firas Mohammed (Infiniscale): Mathematical and Semi-physical compact modeling for emerging technologies
• Heinz Olaf Müller (Plastic Logic): Device simulation for Organic Electronics using Genius

Besides, on June 29 1016, a Workshop on Flexible Electronics will be organized, too. Attendees to TCCM who work on Flexible Electronics (not necessarily modeling) will have a chance to present recent results on their own. 

Finally, on June 30-July 1 we will organize the Annual Graduate Student Meeting on Electronic Engineering, consisting of plenary talks by prestigious researchers and student presentations. 

[more about DOMINO H2020 project at ww.domino-rise.eu]

New i-MOS Release

http://i-mos.org/
A new release of the interactive Modeling and On-line Simulation Platform (i-MOS), version 201401 is available online. In this release, the i-MOS team launched several new services, as well as improved some modules in previous versions. A list of these new features follows:

• Evaluative support for BSIM3 with newly designed interfaces;
• A collection of model parameter cards for your applications;
• A newly implemented double-gate/FinFET model SDDGM; 
• Parameter searching function for all the device models;
• Integrated text editor for composing netlists in circuit simulations;
• Easier entry for your posting of news and events, etc.

For more details and an updated user manual, please see http://i-mos.org

Other related compact/SPICE modeling events and news are listed at:
http://i-mos.org/imos/resources