SSCS Members Who Are 2017 IEEE Fellows

SSCS members who are IEEE Fellows pose with SSCS President, Jan Van der Spiegel and IEEE President, Karen Bartelson at ISSCC 2017. From left to right- Jan Van der Spiegel, Zhihua Wang, Andrei Vladimirescu, Carlo Samori, Borivoje Nikolic, Junichi Nakamura, Deog-kyoon Jeong, Hideto Hidaka, Payam Heydari, Edoardo Charbon, and Karen Bartleson 

How to pick a #winning #IoT #business #model https://t.co/YjMfxPAEZB https://t.co/SDOt080Ka6

How to pick a #winning #IoT #business #model https://t.co/YjMfxPAEZB http://pic.twitter.com/SDOt080Ka6

— Wladek Grabinski (@wladek60) October 30, 2017

from Twitter https://twitter.com/wladek60

October 30, 2017 at 03:39PM
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FOSDEM 2018 CAD and Open Hardware Devroom Call for Participation

(Also visible at https://www.ohwr.org/projects/ohr-meta/wiki/FOSDEM2018)

This is the call for participation in the FOSDEM 2018 devroom on Computer Aided Design (CAD) tools and Open Hardware, to be held on Saturday 3 February 2018 in Brussels, Belgium. We are looking for contributions under the form of talks and tutorials covering the following main topics:

• Printed Circuit Board (PCB) design tools (e.g. KiCad and gEDA)
• Analogue and digital simulators (e.g. ngspice, Qucs, Gnucap, Xyce,GHDL, Icarus and Verilator)
• Any other EDA tools such as high-level tools for digital hardware design (e.g. Migen) and HDL synthesis tools (e.g. Yosys)
• Field solvers such as openEMS
• Mechanical 2D and 3D CAD tools such as LibreCAD, FreeCAD, OpenSCAD andSolveSpace
• Open Hardware projects such as the Teres laptop and the lowRISC SoC
• Inter-project opportunities for collaboration

We hope to provide an opportunity for attendees to bring themselves up to date on the latest FOSS CAD and Open Hardware developments, share knowledge and identify opportunities to collaborate on development tasks. This devroom is an evolution of the EDA devroom we organised in 2015, 2016 and 2017.

The submission process: Please submit your proposals at

https://penta.fosdem.org/submission/FOSDEM18 before 1 December 2017.

If you already have a Pentabarf account (for example as a result of having submitted a proposal in the past), make sure you use it to log in and submit your proposal. Do not create a new account if you already have one. Please provide a bit of information about yourself under Person -> Description -> Abstract. When you submit your proposal (creating an "Event" in Pentabarf), make sure you choose the "CAD and Open Hardware Devroom" in the track drop-down menu. Otherwise your proposal might go unnoticed. Fill in at least a title and abstract for the proposed talk and a suggested duration. Bear in mind that a lot of the value in these meetings comes from the discussions, so please be reasonable regarding the duration of the talk.

Important dates

• 1 December 2017: deadline for submission of proposals
• 8 December 2017: announcement of final schedule
• 3 February 2018: devroom day

Recordings: The FOSDEM organisers hope to be able to live-stream and record all the talks. The recordings will be published under the same licence as all FOSDEM content (CC-BY). Only presentations will be recorded, not informal discussions and whatever happens during the lunch break. By agreeing to present at FOSDEM, you automatically give permission to be recorded. The organisers will agree to make exceptions but only for exceptional and well-reasoned cases.

Mailing list: Feel free to subscribe to the mailing list of the CAD and Open Hardware devroom to submit ideas, ask questions and generally discuss about the event:

https://lists.fosdem.org/listinfo/open-hardware-devroom

Spread the word!

#Modeling the Performance of Nano Machined CMOS Transistors for Uncooled IR Sensing https://t.co/p4RnuHkJiZ

#Modeling the Performance of Nano Machined CMOS Transistors for Uncooled IR Sensing https://t.co/p4RnuHkJiZ

— Wladek Grabinski (@wladek60) October 26, 2017

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October 26, 2017 at 11:26AM
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UNIST Researchers Develop Highly Stable #Perovskite #Solar #Cells https://t.co/g1CN5I44r1 #paper... https://t.co/WSUSekJ1ky

UNIST Researchers Develop Highly Stable #Perovskite #Solar #Cells https://t.co/g1CN5I44r1 #paper... https://t.co/WSUSekJ1ky

— Wladek Grabinski (@wladek60) October 25, 2017

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October 25, 2017 at 08:47PM
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UNIST Researchers Develop Highly Stable #Perovskite #Solar #Cells https://t.co/g1CN5I44r1 #paper https://t.co/p6Jr0nPqF1

UNIST Researchers Develop Highly Stable #Perovskite #Solar #Cells https://t.co/g1CN5I44r1 #paper http://pic.twitter.com/p6Jr0nPqF1

— Wladek Grabinski (@wladek60) October 25, 2017

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Novel Superjunction #LDMOS (>950 V) With a Thin Layer #SOI https://t.co/1NqFJ4rAZB #paper https://t.co/LglxkaZ9PP

Novel Superjunction #LDMOS (>950 V) With a Thin Layer #SOI https://t.co/1NqFJ4rAZB #paper https://t.co/LglxkaZ9PP

— Wladek Grabinski (@wladek60) October 25, 2017

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Novel Superjunction #LDMOS (>950 V) With a Thin Layer #SOI https://t.co/1NqFJ4rAZB #paper

Novel Superjunction #LDMOS (>950 V) With a Thin Layer #SOI https://t.co/1NqFJ4rAZB #paper

— Wladek Grabinski (@wladek60) October 25, 2017

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October 25, 2017 at 11:59AM
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A Planar Junctionless FET Using SiC With Reduced Impact of Interface Traps: Proposal and Analysis https://t.co/g3qPsLKIqB #paper

A Planar Junctionless FET Using SiC With Reduced Impact of Interface Traps: Proposal and Analysis https://t.co/g3qPsLKIqB #paper

— Wladek Grabinski (@wladek60) October 25, 2017

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October 25, 2017 at 11:34AM
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Cryogenic characterization of CMOS technologies

A. Beckers, F. Jazaeri, A. Ruffino, C. Bruschini, A. Baschirotto and C. Enz

Cryogenic characterization of 28 nm bulk CMOS technology for quantum computing

47th ESSDERC, Leuven, Belgium, 2017, pp. 62-65.

Abstract: This paper presents the first experimental investigation and physical discussion of the cryogenic behavior of a commercial 28 nm bulk CMOS technology. Here we extract the fundamental physical parameters of this technology at 300,77 and 4.2 K based on DC measurement results. The extracted values are then used to demonstrate the impact of cryogenic temperatures on the essential analog design parameters. We find that the simplified charge-based EKV model can accurately predict the cryogenic behavior. This represents a main step towards the design of analog/RF circuits integrated in an advanced bulk CMOS process and operating at cryogenic temperature for quantum computing control systems [read more...] doi: 10.1109/ESSDERC.2017.8066592

R. M. Incandela, L. Song, H. A. R. Homulle, F. Sebastiano, E. Charbon and A. Vladimirescu

Nanometer CMOS characterization and compact modeling at deep-cryogenic temperatures

47th ESSDERC, Leuven, Belgium, 2017, pp. 58-61.

Abstract: The characterization of nanometer CMOS transistors of different aspect ratios at deep-cryogenic temperatures (4 K and 100 mK) is presented for two standard CMOS technologies (40 nm and 160 nm). A detailed understanding of the device physics at those temperatures was developed and captured in an augmented MOS11/PSP model. The accuracy of the proposed model is demonstrated by matching simulations and measurements for DC and time-domain at 4 K and, for the first time, at 100 mK [read more...] doi: 10.1109/ESSDERC.2017.8066591

#opensource Summit Europe 2017 https://t.co/c1TgRIgzVE https://t.co/RZqPRisbbS

#opensource Summit Europe 2017 https://t.co/c1TgRIgzVE http://pic.twitter.com/RZqPRisbbS

— Wladek Grabinski (@wladek60) October 18, 2017

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October 18, 2017 at 11:41PM
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A Compact QS Terminal Charge and Drain Current #Model for DG Junctionless Transistors and Its Circuit Validation https://t.co/hTsw5blL8f

A Compact QS Terminal Charge and Drain Current #Model for DG Junctionless Transistors and Its Circuit Validation https://t.co/hTsw5blL8f

— Wladek Grabinski (@wladek60) October 17, 2017

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[paper] Accurate diode behavioral model with reverse recovery

Stanislav Banáš^a,b, Jan Divína^b, Josef Dobeš^b, Václav Paňko^a

^aON Semiconductor, SCG Czech Design Center, Department of Design System Technology, 1. maje 2594, 756 61 Roznov pod Radhostem, Czech Republic

^bCzech Technical University in Prague, Faculty of Electrical Engineering, Department of Radioelectronics, Technicka 2, 166 27 Prague 6, Czech Republic

Solid-State Electronics

Volume 139, January 2018, Pages 31–38

https://doi.org/10.1016/j.sse.2017.10.034

Highlights:

• The complex robust time and area scalable Verilog-A model of diode containing reverse recovery effect has been developed.
• Due to implemented reverse recovery effect the model is useful especially for high-speed or high-voltage power devices.
• The model can be used as stand-alone 2-terminal diode or as a parasitic p-n junction of more complex lumped macro-model.
• Two methods of model parameter extraction or model validation have been demonstrated.

ABSTRACT: This paper deals with the comprehensive behavioral model of p-n junction diode containing reverse recovery effect, applicable to all standard SPICE simulators supporting Verilog-A language. The model has been successfully used in several production designs, which require its full complexity, robustness and set of tuning parameters comparable with standard compact SPICE diode model. The model is like standard compact model scalable with area and temperature and can be used as a stand-alone diode or as a part of more complex device macro-model, e.g. LDMOS, JFET, bipolar transistor. The paper briefly presents the state of the art followed by the chapter describing the model development and achieved solutions. During precise model verification some of them were found non-robust or poorly converging and replaced by more robust solutions, demonstrated in the paper. The measurement results of different technologies and different devices compared with a simulation using the new behavioral model are presented as the model validation. The comparison of model validation in time and frequency domains demonstrates that the implemented reverse recovery effect with correctly extracted parameters improves the model simulation results not only in switching from ON to OFF state, which is often published, but also its impedance/admittance frequency dependency in GHz range. Finally the model parameter extraction and the comparison with SPICE compact models containing reverse recovery effect is presented [read more...]

FIG: Solving the recursive calculation of reverse recovery charge

Software #model multi-level #photonic #IC designs https://t.co/24rtqqVTBH

Software #model multi-level #photonic #IC designs https://t.co/24rtqqVTBH

— Wladek Grabinski (@wladek60) October 14, 2017

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October 15, 2017 at 01:05AM
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5 #benefits of contributing to #opensource projects https://t.co/qKsBgkR9Uh

5 #benefits of contributing to #opensource projects https://t.co/qKsBgkR9Uh

— Wladek Grabinski (@wladek60) October 12, 2017

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October 12, 2017 at 09:30AM
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Intern/Student in SW Eng. for Power Management f/m

Job Description: You will be responsible for developing a SW tool enabling an user friendly and efficient framework to program system-on-chip. The flexibility of our power management solution thanks to enhanced customization is indeed a critical asset requiring a reliable tool from programming definition to release. You will be part of an enthusiastic and international system engineering team located in Munich and will get in touch locally with several design and validation teams [read more...]

Your main tasks in this full time position min 5 months up to 12 months will be to:

• Create several functions/add-ons enhancing entry interface
• Develop a compiler to better explore new chip architectures-Integrate compiler output with existing tools
• Implement sanity checkers detecting
• Develop test scenarios and requirements for chip validation
• Contribute to the reporting and documentation for other teams and management

[read more...]

#Linux Now Has its First #OpenSource #RISC-V Processor https://t.co/cdM2NNXBoE

#Linux Now Has its First #OpenSource #RISC-V Processor https://t.co/cdM2NNXBoE

— Wladek Grabinski (@wladek60) October 7, 2017

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October 07, 2017 at 11:33PM
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#Apple #Opensource-d the #iOS Kernel for #ARM CPUs https://t.co/LUUYUnRSm2 https://t.co/91YMe1jKV1

#Apple #Opensource-d the #iOS Kernel for #ARM CPUs https://t.co/LUUYUnRSm2 http://pic.twitter.com/91YMe1jKV1

— Wladek Grabinski (@wladek60) October 5, 2017

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October 05, 2017 at 12:06PM
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[paper] A Novel Reconfigurable sub-0.25V Digital Logic Family Using the Electron-Hole Bilayer TFET

Cem Alper, Jose Luis Padilla, Pierpaolo Palestri, Senior Member, IEEE

and Adrian M. Ionescu, Fellow, IEEE

IEEE Journal of the Electron Devices Society

doi: 10.1109/JEDS.2017.2758018

Abstract: We propose and validate a novel design methodology for logic circuits that exploits the conduction mechanism and the presence of two independently biased gates (”n-gate” and ”p-gate”) of the electron-hole bilayer TFET (EHBTFET). If the device is designed to conduct only under certain conditions e.g. when Vn-gate = VDD and Vp-gate = 0, it then shows an ’XOR-like’ behavior that allows the implementation of certain logic gates with a smaller number of transistors compared to conventional CMOS static logic. This simplifies the design and possibly results in faster operation due to lower node capacitances. We demonstrate the feasibility of the proposed EHBTFET logic for low supply voltage operation using mixed device/circuit simulations including quantum corrections [read more...]

FIG: Sketch of the hetero-gate InGaAs EHBTFET and its circuit symbol.

[mos-ak] [press note] 15th MOS-AK Workshop at ESSDERC/ESSCIRC September 11, 2017 Leuven

Arbeitskreis Modellierung von Systemen und Parameterextraktion

Modeling of Systems and Parameter Extraction Working Group

15th MOS-AK Workshop at ESSDERC/ESSCIRC

September 11, 2017 Leuven

 The MOS-AK Compact Modeling Association, a global compact/SPICE modeling and Verilog-A standardization forum, held its 15th consecutive workshop as an integral engineering event at the ESSDERC/ESSCIRC on September 11, 2017 in Leuven (B). The event was coorganized by Jean-Michel Sallese, EPFL and Daniel Tomaszewski ITE (PL); its technical program was coordinated by Larry Nagel, OEC (USA) and Andrei Vladimirescu, UCB (USA); ISEP (FR) representing the International MOS-AK Board of R&D Advisers. Technical MOS-AK program promotion was provided by the Eurotraining and NEEDS of nanoHUB.org

A group of the international academic researchers and modeling engineers attended 13 technical compact modeling presentations covering full development chain form the nanoscaled technologies thru semiconductor devices modeling to advanced IC design support. The MOS-AK speakers have shared their latest perspectives on compact/SPICE modeling and Verilog-A standardization in the dynamically evolving semiconductor industry and academic R&D. The event featured advanced technical presentations covering compact model development, implementation, deployment and standardization covering full engineering R&D chain: TCAD/processing, device modeling, transistor level IC design support. These contributions were delivered by leading academic and industrial experts [1-12]. The presentations are available online for download at <http://www.mos-ak.org/leuven_2017/>. Selected best presentation will be recommended for further publication in the IJHSES.

The ESSDERC Track4 Devices and Circuit Compact Modeling has followed the MOS-AK workshop. The Track4 has been organized for very first time to highlight importance of the international compact/SPICE modeling R&D and foster its Verilog-A standardization. The ESSDERC Conference participants have attended four subsequent modeling sessions: Cross-Domain Compact Modeling [13-15]; Parameter Extraction [16-19]; Modeling of Emerging Devices [20-23]; Traps and Noise [24-28]. All the conference papers are available at IEEE Xplore and selected best papers will be recommended for further publication in J-EDS.

The MOS-AK Modeling Working Group has various deliverable and initiatives including a book entitled "Open Source TCAD/EDA Tools for Compact Modeling" and an open Verilog-A directory with models and supporting CAD/EDA software. The MOS-AK Association plans to continue its standardization efforts by organizing additional compact modeling meetings, workshops and courses in Europe, USA, India and China throughout 2017/2018 including:

• 10th International MOS-AK Workshop in Silicon Valley (US) Dec. 2017
  
• Spring MOS-AK Workshop in Strasbourg (F) March 2018
  
• 3rd Sino MOS-AK Workshop in Beijing (CN) June, 2018
  
• 16th MOS-AK ESSDERC/ESSCIRC Workshop in Dresden (D) Sept, 2018

About MOS-AK Association:

MOS-AK, an international compact modeling association primarily focused in Europe, to enable international compact modeling R&D exchange in the North/Latin Americas, EMEA and Asia/Pacific Regions. The MOS-AK Modeling Working Group plays a central role in developing a common language among foundries, CAD vendors, IC designers and model developers by contributing and promoting different elements of compact/SPICE modeling and its Verilog-A standardization and related CAD/EDA tools for the compact models development, validation/implementation and distribution. For more information please visit: mos-ak.org

REFERENCES:

MOS-AK/Leuven 2017 Workshop; Sept. 11, 2017

[1] ASCENT: Access to Leading European Nanoelectronics Technology

Jim Greer Tyndall (IRL)

[2] Junctionless Nanowire Transistors Performance: Static and Dynamic Modeling

Marcelo Antonio Pavanello Centro Universitario FEI (BR)

[3] Modeling and Analysis of Full-Chip Parasitic Substrate Currents

Renaud Gillon and Wim Schoenmaker ONSEMI (B), MAGWEL (B)

[4] Small- and large-signal RF modeling of silicon-based substrates

Martin Rack and Jean-Pierre Raskin Université catholique de Louvain (B)

[5] Tunnel FET C-V modeling: Impact of TFET C-V characteristics on inverter circuit performance

Chika Tanaka, Tetsufumi Tanamoto, and Masato Koyama, Toshiba (J)

[6] ASCENT Open Access to 14nm PDKs

T. Chiarella, N. Cordero, O. Faynot, Tyndall (IRL)

[7] Modelling of Surface Traps Effect on Semiconductor Nanowires

Ashkhen Yesayan*, Stepan Petrosyan*, Jean-Michel Sallese** *IRa, Armenia, **EPFL (CH)

[8] Measurement and modelling of specific behaviors in 28nm FD SOI UTBB MOSFETs of importance for analog / RF amplifiers

D. Flandre, V. Kilchytska, B. Kazemi, C. Gimeno and J.-P. Raskin UC Louvain

[9] IEEE EDS Compact Model Standardization

Benjamin Iniguez URV (SP)

[10] Is it possible to reduce the PDK development cost when demand for data is continuously increasing?

Andrej Rumiantsev MPI Corporation

[11] Optimal measurement parameters for accurate time-domain and spectral analyses of RTN

Léopold Van Brandt*, Valeriya Kilchytska*, Jean-Pierre Raskin*, Bertrand Parvais** and Denis Flandre*  *ELEN department, ICTEAM Institute, Université catholique de Louvain **imec

[12] Compact modeling for CMOS technology development and IC design

Daniel Tomaszewski ITE Warszaw (PL)

ESSDERC Trac4: Compact Modeling; Tuesday September 12, 2017 (11:00-12:20)

Cross-Domain Compact Modeling 

Chair: Wladek Grabinski - MOS-AK; Cristell Maneux – LIMS;

[13] INVITED: SPICE Modeling in Verilog-a: Successes and Challenges

Colin McAndrew

[14] SPICE Modeling of Light Induced Current in Silicon with 'generalized' Lumped Devices

Chiara Rossi, Pietro Buccella, Camillo Stefanucci, Jean-Michel Sallese

[15] Total Ionizing Dose Effects on Analog Performance of 28 nm Bulk MOSFETs

Chun-Min Zhang, Farzan Jazaeri, Alessandro Pezzotta, Claudio Bruschini, Gulio Borghello, Serena Mattiazzo

ESSDERC Trac4: Compact Modeling; Tuesday September 12, 2017 (14:00-15:20)

Parameter Extraction 

Chair: Thierry Poiroux - CEA; Marco Bellini – ABB;

[16] Nanometer CMOS Characterization and Compact Modeling at Deep-Cryogenic Temperatures

Rosario Marco Incandela, Lin Song, Harald Homulle, Fabio Sebastiano, Edoardo Charbon, Andrei Vladimirescu

[17] Cryogenic Characterization of 28 nm Bulk CMOS Technology for Quantum Computing

Arnout Beckers, Farzan Jazaeri, Andrea Ruffino, Claudio Bruschini, Andrea Baschirotto, Christian Enz

[18] A New Method for Junctionless Transistors Parameters Extraction

Renan Trevisoli, Rodrigo Doria, Michelly de Souza, Sylvain Barraud, Marcelo Pavanello

[19] Avalanche Compact Model Featuring SiGe HBTs Characteristics Up to BVCBO

Mathieu Jaoul, Didier Céli, Cristell Maneux, Michael Schröter, Andreas Pawlak

ESSDERC Trac4: Compact Modeling; Tuesday September 12, 2017 (16:40-18:00)

Modeling of Emerging Devices 

Chair: Jean-Michel Sallese - EPFL; Daniel Tomaszewski - ITE;

[20] Equivalent Circuit Model for the Electron Transport in 2D Resistive Switching Material Systems

Enrique Miranda, Chengbin Pan, Marco Villena, Na Xiao, Jordi Suñe, Mario Lanza

[21] Analytical Drain Current Model for Schottky-Barrier CNTFETs

Igor Bejenari, Michael Schroter, Martin Claus

[22] A General Circuit Model for Spintronic Devices Under Electric and Magnetic Fields

Meshal Alawein, Hossein Fariborzi

[23] Compact Physical Model of a-IGZO TFTs for Circuit Simulation

Matteo Ghittorelli, Fabrizio Torricelli, Carmine Garripoli, Jan-Laurens van der Steen, Gerwin Gelinck, Sahel Abdinia

ESSDERC Trac4: Compact Modeling; Wednesday September 13, 2017 (14:20-15:40)

Traps and Noise 

Chair: Benjamin Iniguez - URV; Sadayuki Yoshitomi - Toshiba;

[24] Modeling of Dynamic Trap Density Increase for Aging Simulation of Any MOSFET Circuits Mitiko Miura-Mattausch, Hidenori Miyamoto, Hideyuki Kikuchihara, Dondee Navarro, Tapas K. Maiti, Nezam Rohbani

[25] Comprehensive Compact Electro-Thermal GaN HEMT Model

Muhammad Alshahed, Mina Dakran, Lars Heuken, Mohammed Alomari, Joachim Burghartz

[27] Trap-Assisted Carrier Transport Through the Multi-Stack Gate Dielectrics of HKMG nMOS Transistors: a Compact Model

Apoorva Ojha, Nihar Ranjan Mohapatra

[28] A New Verilog-a Compact Model of Random Telegraph Noise in Oxide-Based RRAM for Advanced Circuit Design

Francesco Maria Puglisi, Nicolò Zagni, Luca Larcher, Paolo Pavan

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A Large-Signal Monolayer Graphene Field-Effect Transistor Compact #Model for RF-Circuit Applications https://t.co/zoPkw74IK2

A Large-Signal Monolayer Graphene Field-Effect Transistor Compact #Model for RF-Circuit Applications https://t.co/zoPkw74IK2

— Wladek Grabinski (@wladek60) September 19, 2017

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Conduction Mechanisms in Metal-Base Vertical Organic Transistors by DC and LF-Noise Measurements https://t.co/ZSiOLFMquC #paper

Conduction Mechanisms in Metal-Base Vertical Organic Transistors by DC and LF-Noise Measurements https://t.co/ZSiOLFMquC #paper

— Wladek Grabinski (@wladek60) September 19, 2017

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#Modeling of #Electromechanical Sensors & Systems https://t.co/K40OGzRV4U https://t.co/rdih9lNeei https://t.co/748KTEgqk7

#Modeling of #Electromechanical Sensors & Systems https://t.co/K40OGzRV4U http://pic.twitter.com/rdih9lNeei https://t.co/748KTEgqk7

— Wladek Grabinski (@wladek60) September 19, 2017

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#Modeling of #Electromechanical Sensors & Systems https://t.co/K40OGzRV4U https://t.co/rdih9lNeei

#Modeling of #Electromechanical Sensors & Systems https://t.co/K40OGzRV4U http://pic.twitter.com/rdih9lNeei

— Wladek Grabinski (@wladek60) September 19, 2017

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[paper] Design techniques for low-voltage analog integrated circuits

Matej Rakus, Viera Stopjakova, Daniel Arbet

Institute of Electronics and Photonics, Faculty of Electrical Engineering

and Information Technology Slovak University of Technology in Bratislava, Slovakia,

Journal of ELECTRICAL ENGINEERING, Vol.68 (2017), No.4, 245–255

DOI: 10.1515/jee-2017–0036

ABSTRACT: In this paper, a review and analysis of different design techniques for (ultra) low-voltage integrated circuits (IC) are performed. This analysis shows that the most suitable design methods for low-voltage analog IC design in a standard CMOS process include techniques using bulk-driven MOS transistors, dynamic threshold MOS transistors and MOS transistors operating in weak or moderate inversion regions. The main advantage of such techniques is that there is no need for any modification of standard CMOS structure or process. Basic circuit building blocks like differential amplifiers or current mirrors designed using these approaches are able to operate with the power supply voltage of 600 mV (or even lower), which is the key feature towards integrated systems for modern portable applications.

Fig: Parameter gm/ID versus the normalized drain current. MOS transistor operates in weak inversion (WI) for i_c < 0.1. Strong inversion (SI) is for i_c < 10. Everything in between belongs to the moderate inversion (MI) with center in i_c = 1 

[paper] Principles and Trends in Quantum Nano-Electronics and Nano-Magnetics for Beyond-CMOS Computing

Ian A. Young and Dmitri E. Nikonov 

Components Research, Technology & Manufacturing Group

Intel Corp., Hillsboro, Oregon, USA

ESSDERC/ESSCIRC Leuven Sept.12-14, 2017

Abstract: An analysis of research in quantum nanoelectronics and nanomagnetics for beyond CMOS devices is presented. Some device proposals and demonstrations are reviewed. Based on that, trends in this field are identified. Principles for development of competitive computing technologies are formulated. Results of beyond-CMOS circuit benchmarking are reviewed.

TABLE I: Voltage Limitations For Computation Variables

Principle 1: Beyond-CMOS circuits require CMOS as an integral part. They will work alongside and augment CMOS computing blocks.

Principle 2: Some devices utilize collective states; this confers advantages of non-volatility or more energy efficient operation.

Principle 3: The choice for an optimal beyond-CMOS device will be determined by compatibility with an efficient and effective interconnect.

Principle 4: Low voltage devices – most direct way to low energy operation.

Principle 5: Start benchmarking with bottom up modeling of devices, build up from simple to more complicated circuits.

Principle 6: Majority gates (if easily implemented in a certain technology) enable more efficient circuits, especially for more complex computation functions.

Principle 7: Use electrical interconnects for longer propagation spans.

Principle 8: To convince the wider community, a non- volatile computing paradigm needs to be general enough to prove that it is valid for more than one architecture; while it needs to be specific enough to dispel claims that an essential aspect is missed.

Principle 9: Neuromorphic computing can be done more efficiently with beyond-CMOS circuits.

Conclusions: In summary, we have presented our view on the recent trends in quantum nanoelectronics and nanomagnetics for beyond CMOS devices, and outlined a few principles to make them realize practical computing technologies. We can pose a question for ourselves: What are the most promising directions of research? Where to double down on the effort? Among many equally important thrusts, our subjective preference is for magnetoelectric switching and neuromorphic beyond-CMOS circuits.

[book] Systematic Design of Analog CMOS Circuits

Paul G. A. Jespers, Boris Murmann
Cambridge University Press; 31 Oct 2017; 342pp

Discover a fresh approach to efficient and insight-driven analog integrated circuit design in nanoscale-CMOS with this hands-on guide. Expert authors present a sizing methodology that employs SPICE-generated lookup tables, enabling close agreement between hand analysis and simulation. This enables the exploration of analog circuit tradeoffs using the gm/ID ratio as a central variable in script-based design flows, and eliminates time-consuming iterations in a circuit simulator. Supported by downloadable MATLAB code, and including over forty detailed worked examples, this book will provide professional analog circuit designers, researchers, and graduate students with the theoretical know-how and practical tools needed to acquire a systematic and re-use oriented design style for analog integrated circuits in modern CMOS.

Current state of the art in #modeling heating effects in nanoscale devices - Books - IOPscience https://t.co/E0UlkDDJVk

Current state of the art in #modeling heating effects in nanoscale devices - Books - IOPscience https://t.co/E0UlkDDJVk

— Wladek Grabinski (@wladek60) September 11, 2017

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#2D Semiconductor Process and Device Simulator #MicroTec: #modeling Development Status Update... https://t.co/OycWKSCKXj

#2D Semiconductor Process and Device Simulator #MicroTec: #modeling Development Status Update... https://t.co/OycWKSCKXj

— Wladek Grabinski (@wladek60) August 31, 2017

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#2D Semiconductor Process and Device Simulator #MicroTec: #modeling Development Status Update… https://t.co/fZy9zm34yX

#2D Semiconductor Process and Device Simulator #MicroTec: #modeling Development Status Update https://t.co/do3ZxocZ5z http://pic.twitter.com/h11HndXXX5

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[paper] Surface Potential Equation for Low Effective Mass Channel Common Double-Gate MOSFET

Ananda Sankar Chakraborty and Santanu Mahapatra, Senior Member, IEEE

in IEEE Transactions on Electron Devices

vol. 64, no. 4, pp. 1519-1527, April 2017

doi: 10.1109/TED.2017.2661798

Abstract: Formulation of accurate yet computationally efficient surface potential equation (SPE) is the fundamental step toward developing compact models for low effective mass channel quantum well MOSFETs. In this paper, we propose a new SPE for such devices considering multisubband electron occupancy and oxide thickness asymmetry. Unlike the previous attempts, here, we adopt purely physical modeling approaches (such as without mixing the solutions from finite and infinite potential wells or using any empirical model parameter), while preserving the mathematical complexity almost at the same level. Gate capacitances calculated from the proposed SPE are shown to be in good agreement with numerical device simulation for wide range of channel thickness, effective mass, oxide thickness asymmetry, and bias voltages [read more...]

FIG: Total gate capacitance per unit width Cgg (Vg) for 7-nm-thick device with 100% asymmetry in front and back oxide thicknesses. nmax = 2. Line = model. Symbol = TCAD

levmar : Levenberg-Marquardt nonlinear least squares algorithms in C/C++

Introduction page: <http://users.ics.forth.gr/~lourakis/levmar/> 

The site provides GPL native ANSI C implementations of the Levenberg-Marquardt optimization algorithm, usable also from C++, Matlab, Perl, Python, Haskell and Tcl and explains their use. Both unconstrained and constrained (under linear equations, inequality and box constraints) Levenberg-Marquardt variants are included. The Levenberg-Marquardt (LM) algorithm is an iterative technique that finds a local minimum of a function that is expressed as the sum of squares of nonlinear functions. It has become a standard technique for nonlinear least-squares problems and can be thought of as a combination of steepest descent and the Gauss-Newton method. When the current solution is far from the correct one, the algorithm behaves like a steepest descent method: slow, but guaranteed to converge. When the current solution is close to the correct solution, it becomes a Gauss-Newton method.

Interfaces for using levmar from high-level programming environments & languages such as Matlab, Perl Python, Haskell and Tcl are also available; please refer to the FAQ for more details.

VALint: the NEEDS Verilog-A Checker

By Xufeng Wang¹, Geoffrey Coram², Colin McAndrew³

1. Purdue University 2. Analog Devices, Inc. 3. Freescale Semiconductor

Version 1.0.0 - published on 31 Mar 2017

doi:10.4231/D3HX15S0V

Abstract: VALint is the NEEDS created, automatic Verilog-A code checker. Its purpose is to check the quality of the Verilog-A code and provide the author feedback if bad practices, common mistakes, pitfalls, or inefficiencies are found. This VALint is published as a standalone tool for the compact model community. It is also built-in as an integrated part of the NEEDS publishing platform [read more...]

[paper] Nanoscale MOSFET Modeling

 Nanoscale MOSFET Modeling: 
Part 1: The Simplified EKV Model for the Design of Low-Power Analog Circuits

C. Enz, F. Chicco and A. Pezzotta

in IEEE Solid-State Circuits Magazine, vol. 9, no. 3, pp. 26-35, Summer 2017

doi: 10.1109/MSSC.2017.2712318

Abstract: This article presents the simplified charge-based Enz-Krummenacher-Vittoz (EKV) [11] metal-oxide-semiconductor field-effect transistor (MOSFET) model and shows that it can be used for advanced complementary metal-oxide-semiconductor (CMOS) processes despite its very few parameters. The concept of an inversion coefficient (IC) is first introduced as an essential design parameter that replaces the overdrive voltage V_G-V_T0 and spans the entire range of operating points from weak via moderate to strong inversion (SI), including the effect of velocity saturation (VS). The simplified model in saturation is then presented and validated for different 40- and 28-nm bulk CMOS processes. A very simple expression of the normalized transconductance in saturation, valid from weak to SI and requiring only the VS parameter mc, is described. The normalized transconductance efficiency G_m/I_D, which is a key figure-of-merit (FoM) for the design of low-power analog circuits, is then derived as a function of IC including the effect of VS. It is then successfully validated from weak to SI with data measured on a 40-nm and two 28-nm bulk CMOS processes. It is then shown that the normalized output conductance G_ds/I_D follows a similar dependence with IC than the normalized G_m/I_D characteristic but with different parameters accounting for drain induced barrier lowering (DIBL). The methodology for extracting the few parameters from the measured I_D-V_G and I_D-V_D characteristics is then detailed. Finally, it is shown that the simplified EKV model can also be used for a fully depleted silicon on insulator (FDSOI) and Fin-FET 28-nm processes [read more...]

FIG: The simplified EKV model applied to a 28-nm FDSOI CMOS process: 

G_m n U_T / I_D versus IC for three different transistor channel lengths

References

[1] A. Bahai, “Ultra-low energy systems: Analog to information,” in Proc. European Solid-State Circ. Conf., Sept. 2016, pp. 3–6.

[2] D. Binkley, Tradeoffs and Optimization in Analog CMOS Design. Hoboken, NJ: Wiley, 2008.

[3] W. Sansen, Analog Design Essentials. New York: Springer-Verlag, 2006.

[4] A. Mangla, M. A. Chalkiadaki, F. Fadhuile, T. Taris, Y. Deval, and C. C. Enz, “Design methodology for ultra low-power analog circuits using next generation BSIM6 MOSFET compact model,” Microelectr. J., vol. 44, no. 7, pp. 570–575, July 2013.

[5] Y. S. Chauhan, S. Venugopalan, M. A. Chalkiadaki, M. A. U. Karim, H. Agarwal, S. Khandelwal, N. Paydavosi, J. P. Duarte, C. C. Enz, A. M. Niknejad, and C. Hu, “BSIM6: Analog and RF compact model for bulk MOSFET,” IEEE Trans. Electron Dev., vol. 61, no. 2, pp. 234–244, Feb. 2014.

[6] C. Enz, M. A. Chalkiadaki, and A. Mangla, “Low-power analog/RF circuit design based on the inversion coefficient,” in Proc. European Solid-State Circ. Conf., Sept. 2015, pp. 202–208.

[7] C. Enz and A. Pezzotta, “Nanoscale MOSFET modeling for the design of low-power analog and RF circuits,” in Proc. Int. Conf. MIXDES, June 2016, pp. 21–26.

[8] W. Sansen, “Analog CMOS from 5 micrometer to 5 nanometer,” in Proc. IEEE Int. Solid State Circuits Conf. Dig. Tech. Papers, Feb. 2015, pp. 1–6.

[9] W. Sansen, “Analog design procedures for channel lengths down to 20 nm,” in Proc. IEEE 20th Int. Conf. Electronics, Circuits, and Systems, Dec. 2013, pp. 337–340.

[10] C. C. Enz and E. A. Vittoz, Charge-Based MOS Transistor Modeling - The EKV Model for Low-Power and RF IC Design. Hoboken, NJ: Wiley, 2006.

[11] C. C. Enz, F. Krummenacher, and E. A. Vittoz, “An analytical MOS transistor model valid in all regions of operation and dedicated to low-voltage and low-current applications,” Analog Integr. Circuits Signal Process. J., vol. 8, pp. 83–114, July 1995.

[12] P. Heim, S. R. Schultz, and M. A. Jabri, “Technology-independent biasing technique for CMOS analogue micropower implementations of neural networks,” in Proc. Sixth Australian Conf. Neural Networks, Sydney, Australia, 1995, pp. 9–12.

[13] C. C. Enz and E. A. Vittoz, “CMOS low-power analog circuit design,” in EmergingTechnologies: Designing Low Power Digital Systems, R. Cavin and W. Liu, Eds. Piscataway, NJ: IEEE, 1996, pp. 79–133.

[14] E. Vittoz and J. Fellrath, “CMOS analog integrated circuits based on weak inversion operations,” IEEE J. Solid-State Circuits, vol. 12, no. 3, pp. 224–231, June 1977.

[15] A. Mangla, C. C. Enz, and J. M. Sallese, “Figure-of-merit for optimizing the current efficiency of low-power RF circuits,” in Proc. Int. Conf. Mixed Design Integrated Circuits and Systems, June 2011, pp. 85–89.

[16] A. Mangla, “Modeling nanoscale quasi-ballistic MOS transistors,” Ph.D. dissertation, EPFL, Switzerland, Dissertation No. 6385, 2014.

[17] R. R. Troutman and A. G. Fortino, “Simple model for threshold voltage in a short- channel IGFET,” IEEE Trans. Electron. Dev., vol. 24, no. 10, pp. 1266–1268, Oct. 1977.

[18] N. Arora, MOSFET Models for VLSI Circuit Simulation. New York: Springer-Verlag, 1993.

[19] Z. H. Liu, C. Hu, J. H. Huang, T. Y. Chan, M. C. Jeng, P. K. Ko, and Y. C. Cheng, “Threshold voltage model for deep submicrometer MOSFETs,” IEEE Trans. Electron Dev., vol. 40, no. 1, pp. 86–95, Jan. 1993.

[20] M. A. Chalkiadaki, “Characterization and modeling of nanoscale MOSFET for ultra-low power RF IC design,” Ph.D. dissertation, EPFL, Switzerland, Dissertation No. 7030, 2016.

Physics-Based Multi-Bias RF Large-Signal GaN HEMT #Modeling and Parameter Extraction Flow - IEEE Xplore Document... https://t.co/tT8gOLBa9k

Physics-Based Multi-Bias RF Large-Signal GaN HEMT #Modeling and Parameter Extraction Flow - IEEE Xplore Document... https://t.co/tT8gOLBa9k

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Physics-Based Multi-Bias RF Large-Signal GaN HEMT #Modeling and Parameter Extraction Flow - IEEE Xplore Document… https://t.co/xwC7X2oxYm

Physics-Based Multi-Bias RF Large-Signal GaN HEMT #Modeling and Parameter Extraction Flow - IEEE Xplore Document https://t.co/sds4WvM9TZ http://pic.twitter.com/EmSfD8SUZO

— Wladek Grabinski (@wladek60) August 25, 2017

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An Analytical #Model for the Gate C–V Characteristics of UTB III—V-on-Insulator MIS Structure - IEEE Xplore... https://t.co/Fe1Fqwu5BJ

An Analytical #Model for the Gate C–V Characteristics of UTB III—V-on-Insulator MIS Structure - IEEE Xplore... https://t.co/Fe1Fqwu5BJ

— Wladek Grabinski (@wladek60) August 25, 2017

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An Analytical #Model for the Gate C–V Characteristics of UTB III—V-on-Insulator MIS Structure - IEEE Xplore Documen… https://t.co/oeYfcvWNvI

An Analytical #Model for the Gate C–V Characteristics of UTB III—V-on-Insulator MIS Structure - IEEE Xplore Document https://t.co/W0W0Yhy0Ci http://pic.twitter.com/bWq1erxitj

— Wladek Grabinski (@wladek60) August 25, 2017

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Modeling and simulation of biological systems using SPICE language

Morgan Madec¹, Christophe Lallement¹, Jacques Haiech²

¹ICube, UMR7357, CNRS / Université de Strasbourg, France

²LIT, UMR 7200, CNRS / Université de Strasbourg, France

Published: August 7, 2017
doi: 10.1371/journal.pone.0182385

Abstract: The article deals with BB-SPICE (SPICE for Biochemical and Biological Systems), an extension of the famous Simulation Program with Integrated Circuit Emphasis (SPICE). BB-SPICE environment is composed of three modules: a new textual and compact description formalism for biological systems, a converter that handles this description and generates the SPICE netlist of the equivalent electronic circuit and NGSPICE which is an open-source SPICE simulator. In addition, the environment provides back and forth interfaces with SBML (System Biology Markup Language), a very common description language used in systems biology. BB-SPICE has been developed in order to bridge the gap between the simulation of biological systems on the one hand and electronics circuits on the other hand. Thus, it is suitable for applications at the interface between both domains, such as development of design tools for synthetic biology and for the virtual prototyping of biosensors and lab-on-chip. Simulation results obtained with BB-SPICE and COPASI (an open-source software used for the simulation of biochemical systems) have been compared on a benchmark of models commonly used in systems biology. Results are in accordance from a quantitative viewpoint but BB-SPICE outclasses COPASI by 1 to 3 orders of magnitude regarding the computation time. Moreover, as our software is based on NGSPICE, it could take profit of incoming updates such as the GPU implementation, of the coupling with powerful analysis and verification tools or of the integration in design automation tools (synthetic biology).

GeNeDA results from the collaboration between three laboratories:
The Laboratory of Engineering Sciences, Computer Sciences and Imaging, ICube, UMR7357, CNRS / Université de Strasbourg, France (Morgan MADEC, Yves GENDRAULT, Elise ROSATI and Christophe LALLEMENT)
The Laboratory of Therapeutic Innovation, LIT, UMR 7200, CNRS / Université de Strasbourg, France (Jacques HAIECH)
The Laboratory of Computer Sciences of Paris 6, LIP6, UMR7606, CNRS / Université Pierre et Marie Curie, Paris, France (François PECHEUX)

Relared papers has been published recently
[1] M. Madec, F. Pêcheux, Y. Gendrault, E. Rosati, C. Lallement and J. Haiech, "GeNeDA: An Open-Source Workflow for Design Automation of Gene Regulatory Networks Inspired from Microelectronics", Journal of Computational Biology, June 2016. doi:10.1089/cmb.2015.0229.
[2] M. Madec et al., "Reuse of Microelectronics Software for Gene Regulatory Networks Design Automation", 1st international conference of the GDB BioSynSys, Paris (FR), Sept. 2016.
[3] M. Madec et al., "EDA inspired Open-source Framework for Synthetic Biology", IEEE 2013 BioCAS Conference, Rotterdam (NL), Nov. 2013.

Germany’s RWTH Aachen University and AMO launch joint Aachen Graphene & 2D-Materials Center

RWTH Aachen University and AMO GmbH in Germany have launched a new joint research center with a focus on efficiently bridging the gap between fundamental science and applications within graphene and related materials-based electronics and photonics.

Sharing the vision of bringing graphene and related materials research from the lab into applications, the five founding principal investigators of the Aachen Graphene and 2D-Materials Center (who are also all members of the EU-funded Graphene Flagship project) are professor Christoph Stampfer (of RWTH, and spokesman for the center), professor Max Lemme (of AMO and RWTH), professor Markus Morgenstern (of RWTH), professor Renato Negra (of RWTH) and Dr Daniel Neumaier (of AMO).

“The center will help to turn the exciting properties of graphene and 2D [two-dimensional] materials into true functions, making these materials not only fascinating for scientists but also serving society,” said Christoph Stampfer following the center’s kick-off meeting on 24 July. “With the Aachen Graphene and 2D-Material Center, we aim at increasing the visibility of Aachen as an excellent place to undertake graphene and 2D material research with both a fundamental and applied focus.”

The center enables the integration of the already ongoing work from RWTH Aachen University and AMO under a legal framework that allows for full collaboration between the groups. In particular, the center will focus on addressing the challenges of future technology including high-frequency electronics, flexible electronics, energy-efficient sensing, photonics as well as spintronics and valleytronics with graphene and related materials and their heterostructures.

Founding Members of the Aachen Graphene and 2D Materials Center:

• Prof. Christoph Stampfer, RWTH Aachen University (Spokesman)
• Prof. Max Lemme, RWTH Aachen University/AMO GmbH
• Prof. Markus Morgenstern , RWTH Aachen University
• Prof. Renato Negra, RWTH Aachen University
• Dr. Daniel Neumaier, AMO GmbH

Performance Assessment of A Novel Vertical Dielectrically Modulated TFET-Based Biosensor - IEEE Xplore #paper https://t.co/jRvJS3MUTs

Performance Assessment of A Novel Vertical Dielectrically Modulated TFET-Based Biosensor - IEEE Xplore #paper https://t.co/jRvJS3MUTs

— Wladek Grabinski (@wladek60) August 19, 2017

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A Threshold Voltage #Model of Tri-Gate Junctionless Field-Effect Transistors Including Substrate Bias Effects https://t.co/sEviQXJbB3

A Threshold Voltage #Model of Tri-Gate Junctionless Field-Effect Transistors Including Substrate Bias Effects https://t.co/sEviQXJbB3

— Wladek Grabinski (@wladek60) August 18, 2017

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[paper] Improvements to a compact MOSFET model for design by hand

Improvements to a compact MOSFET model for design by hand

A. de Jesus Costa, F. Martins Cardoso, E. Pinto Santana and A. I. Araújo Cunha

15th IEEE NEWCAS

Strasbourg, France, 2017, pp. 225-228

doi: 10.1109/NEWCAS.2017.8010146

Abstract: In this work, an improved version of the basic structure of a compact MOSFET model and the respective parameters extraction methodology are proposed. The aim of this approach is to increase accuracy in hand calculations for analog circuit design without significantly increasing its complexity. The influences of both inversion level and channel length are considered in the modeling of a few features such as mobility, threshold voltage and onset of saturation. Simple design examples of current sinks and sources are accomplished to compare the basic and the improved models [read more...]

[mos-ak] [Workshop Program] 15th MOS-AK ESSDERC/ESSCIRC Workshop in Leuven Sept.11 2017

15th MOS-AK ESSDERC/ESSCIRC Compact Modeling Workshop

Leuven; Monday Sept.11, 2017 (8:30-17:00)

Workshop Program online http://www.mos-ak.org/leuven_2017/ 

Together with International MOS-AK Board of R&D Advisers: Larry Nagel, Omega Enterprises Consulting (USA), Andrei Vladimirescu, UCB (USA); ISEP (FR) and Jean-Michel Sallese, EPFL (CH), Daniel Tomaszewski, ITE (PL), MOS-AK Technical Program Coordinators as well as all the Extended MOS-AK TPC Members, we have pleasure to invite to the 15th consecutive MOS-AK workshop organized as an integral part of the ESSDERC/ESSCIRC Conferences in Leuven on Sept.11, 2017. The MOS-AK workshop is organized with aims to strengthen a network and discussion forum among experts in the field, enhance open platform for information exchange related to the compact/SPICE modeling and its Verilog-A standardization, bring people in the compact modeling field together, as well as obtain feedback from technology developers, circuit designers, and CAD/EDA tool developers and vendors. 

Final Program of 15th MOS-AK ESSDERC/ESSCIC Workshop is available online:

http://www.mos-ak.org/leuven_2017/

Venue: 

KU LEUVEN Campus of Social Sciences 

(Parkstraat 45, 3000 Leuven) 

room AV 91.12

Online MOS-AK/Leuven Workshop Registration:

http://www.esscirc-essderc2017.org/howtoregister

(any related inquiries can be sent to register@mos-ak.org)

The MOS-AK workshop will be followed by four session of the ESSDERC Track4 "Device and Circuit Compact Modeling". These four lecture sessions include one invited and 14 pear reviewed papers in the compact/SPICE modeling and Verilog-A standardization domain:

Tuesday September 12, 2017 (11:00-12:20)

Cross-Domain Compact Modeling  

Chair: Wladek Grabinski - MOS-AK; Cristell Maneux - U-Bordeaux;

Tuesday September 12, 2017 (14:00-15:20)

Parameter Extraction  

Chair: Thierry Poiroux - CEA

Tuesday September 12, 2017 (16:40-18:00)

Modeling of Emerging Devices  

Chair: Jean-Michel Sallese - EPFL; Daniel Tomaszewski - ITE;

Wednesday September 13, 2017 (14:20-15:40)

Traps and Noise  

Chair: Benjamin Iniguez - URV; Sadayuki Yoshitomi - Toshiba;

MOS-AK Postworkshop Publications:

Selected best MOS-AK technical presentation will be recommended for further publication

in a special issue of the International Journal of High Speed Electronics and Systems 

Extended MOS-AK Committee

WG170817

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Review of commercial SiC MOSFET models: Topologies and equations - IEEE Xplore #paper https://t.co/LS090HojeE

Review of commercial SiC MOSFET models: Topologies and equations - IEEE Xplore #paper https://t.co/LS090HojeE

— Wladek Grabinski (@wladek60) August 16, 2017

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[paper] Compact Electro-Mechanical-Fluidic Model for Actuated Fluid Flow System

Compact Electro-Mechanical-Fluidic Model for Actuated Fluid Flow System

T. K. Maiti, Member, IEEE, L. Chen, H. Zenitani, H. Miyamoto, Member, IEEE,

M. Miura-Mattausch, Fellow, IEEE, and H. J. Mattausch, Senior Member, IEEE

in IEEE Journal on Multiscale and Multiphysics Computational Techniques, 

vol. 2, no. , pp. 124-133, 2017.

doi: 10.1109/JMMCT.2017.2731878

Abstract: This paper presents a compact electro-mechanical-fluidic system-modeling method for multidomain system simulation based on multidomain physics that considers the total energy conservation condition, in terms of respective potential and flow quantities. Models for electrical, mechanical, and fluidic domains are developed to design the example of a blood pumping system, where the blood flow is driven by electrically controlled organic actuators. The electrical domain includes an organic mosfet-based control circuit, the mechanical domain includes organic actuators, and the fluidic domain includes a flexible fluid-flow channel. Control circuit, actuators, and fluid models are coupled through equivalent circuits, where interconnection relationships between two neighboring domains are expressed using the energy conservation concept. The model accuracy is verified with finite element method (FEM) based numerical simulation. Significantly faster simulation speed than with FEM and good accuracy were achieved [read more...]

TABLE: CORRESPONDING FORCE AND FLOW EQUATIONS FOR ELECTRICAL AND
MECHANICAL DOMAINS ARE SUMMARIZED [21]-[23]

[21] S. D. Senturia, Microsystems Design. Norwell, MA: Kluwer Academic Publisher, 2001.

[22] T. K. Maiti, L. Chen, H. Miyamoto, M. Miura-Mattausch, and H. J. Mattausch, “Modeling of electrostatically actuated fluid flow system for mixed-domain simulation,” in 20th Int. Conf. on Simulation of Semiconductor Processes and Devices (SISPAD), pp. 190-193, Sept. 2015, USA.

[23] T. K. Maiti, L. Chen, H. Miyamoto, M. Miura-Mattausch, and H. J. Mattausch, “Mixed domain compact modeling framework for fluid flow driven by electrostatic organic actuators,” in 45th European Solid-State Device Research Conference (ESSDERC), pp. 52-55, Sept. 2015, Austria. 

A General and Transformable #Model Platform for Emerging Multi-Gate MOSFETs - IEEE Xplore Document https://t.co/q27OgRX5Fd

A General and Transformable #Model Platform for Emerging Multi-Gate MOSFETs - IEEE Xplore Document https://t.co/q27OgRX5Fd

— Wladek Grabinski (@wladek60) August 14, 2017

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Mini-Colloquium (MQ) on Nanoelectronics

AGENDA
DATE: Saturday Aug. 26, 2016

VENUE: IIT Kanpur L16

This Mini-Colloquium (MQ) on Nanoelectronics is being hosted by the IEEE Electron Device Society UP Chapter in collaboration with the Department of Electrical Engineering at IIT Kanpur. Distinguished speakers from renowned universities will be presenting on wide range of topics in Nanoelectronics. The MQ will be organized into 1 hour talks by the speakers. The agenda would be as follows:

Time	Topic	Speaker
9:00 - 9:15	Inauguration
9:15 - 9:30	High Tea
9:30 - 10:30	Nanotransistors with 2D materials: Opportunities and Challenges	Prof. Navkanta Bhat IISc
10:30 - 11:30	Revisiting gate C-V characterization for high mobility semiconductor MOS devices	Prof. Anisul Haque East West Univ.
11:30 - 11:45	Tea
11:45 - 12:45		Prof. V. Ramgopal Rao IIT Delhi
12:45 - 14:15	Lunch
14:15 - 15:15	ASM-HEMT - First Industry Standard Compact Model for GaN HEMTs	Prof. Yogesh Singh Chauhan IIT Kanpur
15:15 - 16:15	Spintronics - Perspectives and Challenges	Prof. Brajesh Kumar Kaushik IIT Roorkee
16:15 - 16:30	Tea
16:30 - 17:30	Advanced Hetero structure based Nano Scale MOSFETs	Prof. Chandan Kumar Sarkar Jadavpur Univ.

Coordinator: Dr. Yogesh S.Chauhan IIT Kanpur, India
Website: http://www.iitk.ac.in/nanolab/MQ/index.html