SSCS PICO Chronicle

Mirjana Videnovic-Misic, Harald Pretl, Ali Sabir, Zonghao (Chris) Li, 

and Sadayuki Yoshitomi

SSCS PICO Chronicles: news from the open source community

Date of current version: 14 November 2023

DOI: 10.1109/MSSC.2023.3315888

The Growing Activity of Open Source Chip Design in Japan

The Chipathon 2023 Team Japan consists of 12 volunteers from industry and academia. Since the team members are located in different parts of Japan, the team will be working remotely to design the project. On 4 August, they held a kickoff meeting where the members, who had been working together on Slack, gathered for the first time in person. Although many of the team members have no tape-out experience, they are all truly interested in IC design. The leader of Team Japan is Prof. Akira Tsuchiya at the University of Shiga in Japan (FIG).

Prof. Tsuchiya has been working on open source IC design and has been a volunteer member of the SSCS Chipathon since October 2022. He has promoted open source IC design and SSCS PICO activities in Japan. He held several hands-on events, for example, at the summer camp of the IE- ICE ICD in 2022. Also, he gave several talks about open source IC design and his research on analog synthesis in domestic conferences. And now, he has recruited members and applied to the latest Chipathon. Let’s look forward to the activities of the new members of “Team Japan.”

FIG: Prof. Akira Tsuchiya, an associate professor of the University of Shiga prefecture, 

Japan, and a snapshot of the kickoff meeting (hybrid) of the Chipathon 2023 Japan team

[IEEE SSCS] “PICO” Open-Source Chipathon

IEEE SSCS “PICO” Open-Source Chipathon

Automating Analog Layout

https://sscs.ieee.org/about/tc-ose/sscs-pico-design-contest

– Sign-Up Deadline: May 10, 2024 –

The IEEE Solid-State Circuits Society is pleased to announce its fourth open-source integrated circuit (IC) design contest under the umbrella of its PICO Program (Platform for IC Design Outreach). While this contest is open to anyone (no restrictions), we encourage the participation of pre-college students, undergraduates, and geographical regions that are underrepresented within the IC design community. 

The goal of this year’s event is to advance the automatic generation and open sharing of analog circuit layout cells to increase our community’s design productivity and to catch up with other fields where sharing and automation is a key enabler of progress (e.g., in machine learning).

Die photo in background courtesy of IBM

Contest Outline

1. Interested individuals sign up using this form by May 10, 2024.
2. Phase 1 (~June): Through a series of weekly meet-ups and training sessions, the participants learn to create basic one- or two-transistor layout generators using Python and open-source CMOS PDKs. Using Jupyter Notebooks hosted on Google Colab allows anyone with an internet connection to participate - no downloads or installations required! Relevant circuit examples can be found in [1], [2]. We will leverage code modules available with the OpenFASoC [3] environment.
3. Phase 2 (~July): Interested participants define larger layout building blocks that they wish to automate (examples: comparator, bandgap, phase interpolator, OTA). Teaming among participants is encouraged to maximize collaboration and learning).
4. Phase 3 (~August-September): Participants implement their generators and submit sample layouts and test structures for potential tape-out to an open-source MPW (tentatively SKY130).
5. Phase 4 (~October-November): A jury evaluates the created generators/layouts and selects the test structures that will be taped out. The teams work together to assemble a shared database with all the designs and to complete the tapeout. Ideally, this phase will involve automated verification through CACE [4] or a similar tool.
6. Phase 5 (TBD): The designs will be tested using lab measurements by a subset of participants and SSCS volunteers with access to lab facilities. Some of the test setups may be available for remote characterization. The obtained measurement data will be added to the repositories containing the layout generators.

 References

[1] H. Pretl, “Fifty Nifty Variations of Two-Transistor Circuits,” MOS-AK Workshop Spring 2022, URL: https://www.mos-ak.org/spring_2022/presentations/Pretl_Spring_MOS-AK_2022.pdf.
[2] H. Pretl and M. Eberlein, "Fifty Nifty Variations of Two-Transistor Circuits: A tribute to the versatility of MOSFETs," in IEEE Solid-State Circuits Magazine, vol. 13, no. 3, pp. 38-46, Summer 2021, URL: https://ieeexplore.ieee.org/document/9523464.
[3] OpenFASoC: Fully Open-Source Autonomous SoC Synthesis using Customizable Cell-Based Synthesizable Analog Circuits, https://github.com/idea-fasoc/OpenFASOC/.
[4] Circuit Automatic Characterization Engine, URL: https://github.com/efabless/cace.

SSCS April Technical Webinar

SSCS April Technical Webinar

Getting Started with Open Source Silicon, Presented By: Matthew Venn

Abstract: In this presentation, Matt Venn will share his experience of getting started with chip design using the free and open source tools. Going from zero to 20 chips in 3 years, there are plenty of successes and failures to share. Matt will then move on to sharing the best resources, inspirational example projects, and showcase some of his own tools. The presentation will finish with a demonstration showing just how easy and cheap it is to get your own chip manufactured today.

Biography: Matt Venn is a science & technology communicator and electronic engineer. He has been involved with open source silicon for the last 3 years and has sent 20 chips for manufacture. He has helped over 600 people learn the tools, with 300 people taking part in manufacturable designs:

• https://zerotoasiccourse.com/
• https://tinytapeout.com

Date: 2024-04-19 Time: 11 AM ET

Location Webinar - Online

Contact Aeisha VanBuskirk – a.vanbuskirk@ieee.org

Register Here

Commemorative and Networking Event: 75th anniversary of the transistor

IEEE Switzerland Solid State Circuits Chapter

invites you to join the networking event to celebrate

the 75th anniversary of the transistor

Three IEEE Distinguished Lecturers will talk about the transistor history and its properties. It will be followed by short presentations about semiconductor industry activities in Switzerland, with the following networking apéro.

Attendance is free and open to all: mention it and forward to your friends and colleagues.

Please register for logistics reasons. 

Date and Time	Location
Date: 30 Mar 2023 Time: 01:00 PM to 07:30 PM All times are (UTC+01:00) Bern Add Event to Calendar iCal Google Calendar	EPFL Microcity Rue de la Maladière 71C CH-2020 Neuchâtel Room Number: MC A1 272 Click here for Map

Agenda

13:00 – 13:30 Welcome Coffee 

13:30 – 14:15 Tom Lee: From Rocks to Chips: Stories of the Transistor

14:15 – 15:15 Chris Mangelsdorf: Don't try this with CMOS

15:15 – 15:45 Coffee break 

15:45 – 16:30 Christian Enz: The Design of Low-power Analog CMOS Circuits Using the Inversion Coefficient

16:30 – 17:30 Semiconductor industry in Switzerland, sharing experiences 
                        (W.Grabinski, Panel Moderator):

• Bipolar transistor manufacturing in Switzerland – Hugo Wyss
• Integrated Circuits – Eric Vittoz
• Semiconductor design in the 21st century – Alain-Serge Poret
• Micro-electronics for Swiss made products – Evert Dijkstra
• Semiconductor manufacturing equipment – André Gerde

17:30 – 19:00 Apéro riche

Hosts

Switzerland Section Chapter, SSC37 : https://sscs.ieee.ch
Switzerland Section : https://ieee.ch/

IEEE SSCS PICO Contestants Cross the Finish Line

by Boris Murmann

DOI:10.1109/MSSC.2021.3135176

Date of current version: 24 January 2022

Last summer 2021, the IEEE Solid-State Circuits Society (SSCS) launched its first open source chip design contest under the umbrella of its Platform for Integrated Circuit Design Outreach program (PICO). Beginning with 61 submissions, a volunteer jury selected 18 teams from nine countries to embark on a journey toward tapeout. Anyone interested in supporting future activities is encouraged to sign up at the Society’s volunteer web portal. Stay tuned for the 2022 edition of the SSCS PICO contest!

FIG: Layout views of the chips submitted for tape out

      TABLE: A Summary Oof Designs Submitted for TapeOut

	Function	Team	Chip URL
1	5G bidirectional amplifier	Pakistan 3 (National University of Computer and Emerging Sciences)	https://efabless.com/projects/560
2	Wireless power transfer unit	Pakistan 2 (National University of Computer and Emerging Sciences)
3	Variable precision fused multiply–add unit	Pakistan 1 (National University of Computer and Emerging Sciences)
4	Oscillator-based LVDT readout	India 2 (Anna University)	https://efabless.com/projects/474
5	Temperature sensor	India 1 (Anna University)
6	GPS baseband engine	India 3 (Anna University)
7	Ultralow-power analog front end for bio signals	Brazil 2 (Universidade Federal de Santa Catarina)	https://efabless.com/projects/476
8	TIA for quantum photonics interface	USA 4 (University of Virginia)	https://efabless.com/projects/470
9	Bandgap reference	Egypt (Cairo University)	https://efabless.com/projects/473
10	Neural network for sleep apnea detection	USA 2 (University of Missouri)
11	Sonar processing unit	Chile (University of the Bío-Bío)	https://efabless.com/projects/54

SSCS Members Who Are 2017 IEEE Fellows

SSCS members who are IEEE Fellows pose with SSCS President, Jan Van der Spiegel and IEEE President, Karen Bartelson at ISSCC 2017. From left to right- Jan Van der Spiegel, Zhihua Wang, Andrei Vladimirescu, Carlo Samori, Borivoje Nikolic, Junichi Nakamura, Deog-kyoon Jeong, Hideto Hidaka, Payam Heydari, Edoardo Charbon, and Karen Bartleson