[paper] CV of Graphene–Silicon Heterojunction Photodiodes

Sarah Riazimehr,  Melkamu Belete,  Satender Kataria,  Olof Engström and Max Christian Lemme

Capacitance–Voltage (C –V) Characterization 

of Graphene–Silicon Heterojunction Photodiodes

Advanced Optical Materials 

First Published Open Access: 07 May 2020

DOI: 10.1002/adom.202000169

Abstract: Heterostructures of 2D and 3D materials form efficient devices for utilizing the properties of both classes of materials. Graphene/silicon (G/Si) Schottky diodes have been studied extensively with respect to their optoelectronic properties. Here, a method to analyze measured capacitance–voltage (C –V) data of G/Si Schottky diodes connected in parallel with G/silicon dioxide/Si (GIS) capacitors is introduced. The accurate extraction of the built‐in potential (Φbi) and the Schottky barrier height (SBH) from the measurement data independent of the Richardson constant is also demonstrated.

Figure 2

Fig.: a) Cross section of the test device showing both MIS and GIS regions. b) Small‐signal C –V characteristics of Dtest (line) compared to a theoretically calculated C –V curve (dashed ) at 10 kHz.

Acknowledgements: Financial support from the European Commission (Graphene Flagship, 785219, 881603) and the German Ministry of Education and Research, BMBF (GIMMIK, 03XP0210) is gratefully acknowledged.

[paper] Surface Potential Equation for Low Effective Mass Channel Common Double-Gate MOSFET

Ananda Sankar Chakraborty and Santanu Mahapatra, Senior Member, IEEE

in IEEE Transactions on Electron Devices

vol. 64, no. 4, pp. 1519-1527, April 2017

doi: 10.1109/TED.2017.2661798

Abstract: Formulation of accurate yet computationally efficient surface potential equation (SPE) is the fundamental step toward developing compact models for low effective mass channel quantum well MOSFETs. In this paper, we propose a new SPE for such devices considering multisubband electron occupancy and oxide thickness asymmetry. Unlike the previous attempts, here, we adopt purely physical modeling approaches (such as without mixing the solutions from finite and infinite potential wells or using any empirical model parameter), while preserving the mathematical complexity almost at the same level. Gate capacitances calculated from the proposed SPE are shown to be in good agreement with numerical device simulation for wide range of channel thickness, effective mass, oxide thickness asymmetry, and bias voltages [read more...]

FIG: Total gate capacitance per unit width Cgg (Vg) for 7-nm-thick device with 100% asymmetry in front and back oxide thicknesses. nmax = 2. Line = model. Symbol = TCAD

Mini-Colloquium (MQ) on Nanoelectronics

AGENDA
DATE: Saturday Aug. 26, 2016

VENUE: IIT Kanpur L16

This Mini-Colloquium (MQ) on Nanoelectronics is being hosted by the IEEE Electron Device Society UP Chapter in collaboration with the Department of Electrical Engineering at IIT Kanpur. Distinguished speakers from renowned universities will be presenting on wide range of topics in Nanoelectronics. The MQ will be organized into 1 hour talks by the speakers. The agenda would be as follows:

Time	Topic	Speaker
9:00 - 9:15	Inauguration
9:15 - 9:30	High Tea
9:30 - 10:30	Nanotransistors with 2D materials: Opportunities and Challenges	Prof. Navkanta Bhat IISc
10:30 - 11:30	Revisiting gate C-V characterization for high mobility semiconductor MOS devices	Prof. Anisul Haque East West Univ.
11:30 - 11:45	Tea
11:45 - 12:45		Prof. V. Ramgopal Rao IIT Delhi
12:45 - 14:15	Lunch
14:15 - 15:15	ASM-HEMT - First Industry Standard Compact Model for GaN HEMTs	Prof. Yogesh Singh Chauhan IIT Kanpur
15:15 - 16:15	Spintronics - Perspectives and Challenges	Prof. Brajesh Kumar Kaushik IIT Roorkee
16:15 - 16:30	Tea
16:30 - 17:30	Advanced Hetero structure based Nano Scale MOSFETs	Prof. Chandan Kumar Sarkar Jadavpur Univ.

Coordinator: Dr. Yogesh S.Chauhan IIT Kanpur, India
Website: http://www.iitk.ac.in/nanolab/MQ/index.html

[Summer Tutorial] Verified Measurements for Successful Device Models

 Verified Measurements for Successful Device Models 

 at IHP in Frankfurt (Oder), June 15-17, 2016 

Good electronic device modeling results depend directly on reliable, qualified and verified measurements. It is a known fact that problems with device models are – to a big part – rather due to measurement problems. Within the measurement chain of DC, Impedance (CV), S-Parameter, Nonlinear RF, and Noise, there are several challenges to overcome like device self-heating, contact resistance, max. applicable RF power, calibration, de-embedding etc.

IHP Summer Tutorial will take place at IHP in Frankfurt (Oder), June 15-17, 2016. It will cover in detail all these measurement domains, will explain the setups, the data verification methods, the traps to be avoided, and give best-practice recommendations and examples. It will be enhanced by live measurements in IHP’s measurement labs.

As a wrap-up, an introduction into device modeling, applying the qualified and verified measurements, will be given at the end.

Who should attend: Semiconductor manufacturing and measurement engineers, device modeling engineers, scientists and students working/interested in measurement techniques.

[Course Schedule]