Cem Alper, Jose Luis Padilla, Pierpaolo Palestri, Senior Member, IEEE
and Adrian M. Ionescu, Fellow, IEEE
IEEE Journal of the Electron Devices Society
doi: 10.1109/JEDS.2017.2758018
Abstract: We propose and validate a novel design methodology for logic circuits that exploits the conduction mechanism and the presence of two independently biased gates (”n-gate” and ”p-gate”) of the electron-hole bilayer TFET (EHBTFET). If the device is designed to conduct only under certain conditions e.g. when Vn-gate = VDD and Vp-gate = 0, it then shows an ’XOR-like’ behavior that allows the implementation of certain logic gates with a smaller number of transistors compared to conventional CMOS static logic. This simplifies the design and possibly results in faster operation due to lower node capacitances. We demonstrate the feasibility of the proposed EHBTFET logic for low supply voltage operation using mixed device/circuit simulations including quantum corrections [read more...]
FIG: Sketch of the hetero-gate InGaAs EHBTFET and its circuit symbol.
