Invitation to attend Webinars at Upadhyaya College, University of Delhi

Future symposium/lecture workshops which are chalked under The National Academy of Sciences India (Delhi Chapter) & Deen Dayal Upadhyaya College, University of Delhi Joint Science Promotion Initiative under DBT Star College Program during December 2021 - March 2022. 

Other than these we have planned three School Outreach Programs during December 2021 - January 2022 which shall cover schools within Delhi/NCR and in Uttarakhand.

I request you to kindly forward this email to all Science Students and Teachers of your Institution so that all those who are interested to attend one or more programs should fill the google feedback form through the link: https://docs.google.com/forms/d/e/1FAIpQLScqwQpRG-Vn-Ou3R6lrPYvJRErf6wj62QCsua29DTyRAFvI3w/viewform

Zoom Link will be sent to those who will pre-register using the google form link. No Registration Fees.

E-Certificate of Participation shall be provided to all participants who will fill the feedback form for each webinar.

List of Nobel Laureates and Fellows of Royal Society who have kindly agreed to deliver Invited Talk (Virtual platform) during Jan 2022-March 2022

• Professor Reinhard Genzel, Nobel Laureate 2020, Professor Emeritus, Acting Director, Max Planck Institute for Extraterrestrial Physics
• Professor Sir John Pendry FRS, The Blackett Laboratory, Department of Physics, Imperial College London
• Professor James Durrant, FRS, Faculty of Natural Sciences, Department of Chemistry, Imperial College London, South Kensington Campus, London
• Prof Sir Colin Humphreys, FRS, School of Engineering and Materials Science, Queen Mary University of London
  
• Professor B. Rosemary Grant, FRS, Senior Research Biologist, Emeritus, Department of Ecology and Evolutionary biology, Princeton University
• Professor H. Vincent Poor, FRS, FIEEE, Michael Henry Strater University Professor, Department of Electrical and Computer Engineering, Princeton, New Jersey
• Prof. Tom McLeish, FRS, Professor of Natural Philosophy in the Department of Physics, University of York, Heslington, York, YO10 5DD, UK 
• Professor Thirumalai Venkatesan, FRS, Professor, Condensed Matter Physics, Director, Center for Quantum Research and Technology, The University of Oklahoma
• Prof. Vikram Sudhir Deshpande, FRS, Department of Engineering, Trumpington Street Trumpington Street, Cambridge CB2 1RF, UK
• Professor A.R. Ravishankara, University Distinguished Professor, Departments of Chemistry and Atmospheric Science, Colorado State University, USA
  
• Professor Sriram Ramaswamy, FRS, Department of Physics, Indian Institute of Science, Bengaluru

First International Symposium to Celebrate 75 Years of Invention of the Transistor - Contributions by Scientists of Indian Origin scheduled during December 23, 2021 – December 30, 2021.

• Professor Renuka P. Jindal, IEEE Division I Delegate/Director, 2018, 2019, Founding Editor-in-Chief, IEEE J-EDS & Past President, IEEE Electron Devices Society, Eminent Scientist & Chief Technology Officer, Vanderziel Institute of Science and Technology, LLC, Princeton, NJ
  
• Professor Sanjay Banerjee, Fellow of IEEE, APS and AAAS, Cockrell Family Regents Chair Professor of Electrical and Computer Engineering and Director, Microelectronics Research Center, at the University of Texas, Austin.
• Professor Santosh K. Kurinec, Fellow of IEEE, Department of Electrical and Microelectronic Engineering, Kate Gleason College of Engineering, Rochester Institute of Technology (RIT)
• Dr. Samar Saha, Chief Research Scientist at Prospicient Devices, California, USA and Adjunct faculty in Electrical Engineering (EE) department, Santa Clara University, USA
• Professor Kaustav Banerjee, Fellow-IEEE/APS/JSPS/AAAS, Professor, Electrical and Computer Engineering & Director, Nanoelectronics Research Laboratory; Affiliated Faculty, California NanoSystems Institute and Institute for Energy Efficiency, University of California
  
• Prof. P. Chakrabarti, Director, IIEST Shibpur & Professor (on Deputation), Department of Electronics Engineering, IIT (BHU), Varanasi.
• Dr. Amitava DasGupta, V.V. Sastry Institute Chair Professor, Department of Electrical Engineering, IIT Madras
  
• Professor Udayan Ganguly, Department of Electrical Engineering, IIT Bombay, Powai
• Professor R. Muralidharan, Former Director-Solid State Physics Laboratory
• Professor S. Jit, Department of Electronics Engineering, Indian Institute of Technology (BHU), Varanasi
  
• Professor Nihar Ranjan Mohapatra, Indian Institute of Technology Gandhinagar, India
• Professor Shreepad Karmalkar, Professor, Electrical Engineering  Department, Indian Institute of Technology, Madras
• Professor Swaroop Ganguly, Department of Electrical Engineering, IIT Bombay, Powai
• Professor Sudeb Dasgupta, Head & Professor, Department of Electronics and Communication Engineering, Project Director, DivyaSampark i-Hub Technology Innovation Hub, IIT Roorkee, Indian Institute of Technology, Roorkee

Sixth Lecture Workshop (Online) on Trans-disciplinary Areas ofResearch and Teaching by Shanti Swarup Bhatnagar Awardees to be held during January 2022 - February 2022

• Prof. Avinash K Agarwal, FAAAS, FSAE, FASME, FRSC, FNAE, FNASc, FISEES, J C Bose National Fellow, Department of Mechanical Engineering, Indian Institute of Technology Kanpur
  
• Dr Kayarat Saikrishnan, Biology Division, Indian Institute of Science Education and Research, Pune
• Professor Rajesh Ganapathy, International Centre for Materials Science & School of Advanced Materials, Jawaharlal Nehru Centre for Advanced Scientific Research, Bangalore
• Dr Subhadeep Chatterjee, Laboratory of Plant-Microbe Interactions, Centre for DNA Fingerprinting and Diagnostics, Hyderabad
• Professor Rohit Srivastava, FNASc, FRSC, FRSB, Himanshu Patel Chair Professor and Head, Department of BSBE, IIT Bombay, Powai
• Professor Debdeep Mukhopadhyay, Dept of Computer Sc and Engg, Indian Institute of Technology Kharagpur, West Bengal
• Professor Shankar Ghosh, Dept. of Condensed Matter Physics, Tata Institute of Fundamental Research, Mumbai
• Dr T Govindaraju, Bio-organic Chemistry Laboratory, Jawaharlal Nehru Centre for Advanced Scientific Research, Bengaluru
• Professor Tapas Kumar Maji, PhD, FASc, FRSC, Chemistry and Physics of Materials Unit (CPMU), School of Advanced Materials (SAMat), Jawaharlal Nehru Centre for Advanced Scientific Research(JNCASR), Bangalore
• Professor Anish Ghosh, School of Mathematics, Tata Institute of Fundamental Research, Mumbai
• Professor Subi Jacob George, Chair-New Chemistry Unit (NCU), Faculty at School of Advanced Materials (SAMat), Jawaharlal Nehru Centre for Advanced Scientific Research (JNCASR), Bangalore
• Dr Kanak Saha, Inter-University Centre for Astronomy and Astrophysics, Pune 

Professor Manoj Saxena, MInstP (UK), SMIEEE(USA)

Member-Institute of Physics (UK) Semiconductor Group

Member-The National Academy of Sciences India (NASI)-Delhi Chapter

Former Associate-Indian Academy of Science (IASc)

Member-IEEE Electron Device Society Board of Governor (2018-2020)

Official Homepage

List of Nobel Laureates, Distinguished Experts and Fellows of Royal Society who have delivered Invited Talks (Virtual) during 2020-2021. These were attended by over 9000+ attendees from 30+ Countries. You can watch some of the recordings on https://www.youtube.com/channel/UCNQWWGPD2tySyB5lSo1erLQ

Nobel Laureate Prof. Jean-Marie LEHN, Chemistry 1987 SIS, University of Strasbourg Institute for Advanced Study

Nobel Laureate William D. Phillips, Physics 1997 Quantum Institute, National Institute of Standards and Technology and University of Maryland

Nobel Laureate Sir Anthony J. Leggett, Physics 2003 Professor Emeritus, Department of Physics, Grainger College of Engineering, University of Illinois Urbana-Champaign

Nobel Laureate David Wineland, Physics 2012 Philip H. Knight Distinguished Research Chair & Research Professor, Department of Physics, University of Oregon

Nobel Laureate J. Michael Kosterlitz, Physics 2016 Harrison E. Farnsworth Professor of Physics, Brown University

Nobel Laureate Professor Randy Schekman,  Physiology/Medicine 2013 Howard Hughes Institute Investigator and Professor of Cell and Developmental Biology, University of California, Berkeley

Nobel Laureate Professor Andrea Ghez, Physics 2020 Professor of Physics and Astronomy, University of California, Los Angeles

Professor Malcolm Levitt, Fellow Royal Society (UK) FRS School of Chemistry at the University of Southampton

Prof. J. Paul Attfield, FRS, FRSE, FRSC, Foreign Fellow INSA Centre for Science at Extreme Conditions and School of Chemistry, University of Edinburgh,

Professor Sir Chris Llewellyn Smith, FRS, FAPS (USA), Honorary Fellow, IOP (UK), Foreign Fellow INSA(India) Rudolf Peierls Centre for Theoretical Physics, Parks Road, Oxford OX1 3PU

Professor Philip K. Maini, FRS, FIMA, FRSB, FMedSci, Foreign Fellow INSA (India) Wolfson Centre for Mathematical Biology, Mathematical Institute, Oxford

Professor Sir Peter Julius Lachmann, FRS, FRCP, FRCPath, FMedSci, Foreign Fellow INSA(India) Fellow, Emeritus Sheila Joan Smith Professor of Immunology, Christ College, University of Cambridge

Professor Marta Kwiatkowska, Fellow Royal Society (UK) Associate Head of MPLS Division Fellow of Trinity College, Department of Computer Science University of Oxford, Oxford

Professor Eli Yablonovitch, Fellow Royal Society (UK) The James & Katherine Lau Engineering  Chair Professor, Electrical Engineering & Computer Sciences Dept., Director of the NSF Center for Energy Efficient Electronics Science, E3S Member, Kavli Energy Nano-Sciences Institute at Berkeley Senior Faculty Scientist, Lawrence Berkeley National Laboratory University of California, Berkeley

Professor Molly S. Shoichet, Fellow Royal Society (UK) Tier 1 Canada Research Chair in Tissue Engineering, Professor of Chemical Engineering & Applied Chemistry and Biomaterials & Biomedical Engineering. Donnelly Centre for Cellular & Biomolecular Research, University of Toronto

Professor Julia Yeomans,  Fellow Royal Society (UK) The Rudolf Peierls Centre for Theoretical Physics, 1 Keble Road, Oxford, OX1 3NP, UK

Professor Mike Lockwood, Fellow Royal Society (UK) Space and Atmospheric Electricity Group, Department of Meteorology, University of Reading, UK

Professor Graham R Fleming, Fellow Royal Society (UK) Professor of Chemistry, Univ. of California Berkeley & Senior Faculty Scientist, Lawrence Berkeley National Laboratory

Professor Sir Richard Friend, Fellow Royal Society (UK) Cavendish Professor of Physics & Director Winton Programme for the Physics of Sustainability, Cavendish Laboratory, Cambridge

Professor Andrew Fabian, FRS Former President – UK's Royal Astronomical Society (2008-2010), Institute of Astronomy, University of Cambridge

Professor Manoj Saxena | आचार्य मनोज  सक्सेना 

Program Coordinator-DBT Star College Program

Department of Electronics | इलेक्ट्रॉनिक्स विभाग

Deen Dayal Upadhyaya College | दीन दयाल उपाध्याय कॉलेज

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Dwarka Sector-3, New Delhi-110078 | द्वारका क्षेत्र -३, नई दिल्ली -११००७८

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[paper] Unified Model of Shot Noise in the Tunneling Current in Sub-10 nm MOSFETs

Jonghwan Lee

Unified Model of Shot Noise in the Tunneling Current in Sub-10 nm MOSFETs

Nanomaterials 2021, 11, 2759

DOI: 10.3390/nano11102759

  

Department of System Semiconductor Engineering, Sangmyung University, Cheonan 31066, Korea,
  

Abstract: A single unified analytical model is presented to predict the shot noise for both the source to drain (SD) and the gate tunneling current in sub-10 nm MOSFETs with ultrathin oxide. Based on the Landauer formula, the model is constructed from the sequential tunneling flows associated with number fluctuations. This approach provides the analytical formulation of the shot noise as a function of the applied voltages. The model performs well in predicting the Fano factor for shot noise in the SD and gate tunneling currents.

Fig: Comparison between ST model and CT model of Fano factor as a function of Vgs

for (a) SD current noise and (b) gate tunneling current noise.

Funding: This work was supported by the National Research Foundation of Korea (NRF) grant funded by the Korea government (MSIT) (No. 2019R1F1A1050640).

[paper] Charge-based Modeling of FETs

Jean-Michel Sallese 

Charge-based modeling of field effect transistors, Make it easy

Joint International EUROSOI and EuroSOI-ULIS Workshop (Sept.2020)

DOI: 10.1109/EuroSOI-ULIS53016.2021.956068

 
EDLab, EPFL,  Lausanne  (CH)
 

Abstract: In this presentation, we revisit some charge voltage dependencies for different architectures of field effect transistor, emphasizing on compactness and simplicity while maintaining a close link with physics, which makes these models predictive and accurate for general purposes of compact modeling.

Fig: The gm/I invariant versus the inversion coefficient IC. 

The operation modes of the MOSFET are clearly defined. 

Acknowledgements: I (JMS) would like to thank F. Jazaeri, C. Lallement, W. Grabinski, B. Iniguez and M. Bucher for their constructive interactions. 

[paper] CMOS floating-gate device for quantum control hardware

Michele Castriotta¹, Enrico Prati², Giorgio Ferrari¹

Cryogenic characterization and modeling of a CMOS floating-gate device 

for quantum control hardware

preprint arXiv:2110.02315, 2021

1 Dipartimento di Elettronica, Informazione e Bioingegneria, Politecnico di Milano (I)
2 Istituto di Fotonica e Nanotecnologie, Consiglio Nazionale delle Ricerche (I)

Abstract - We perform the characterization and modeling of a floating gate device realized with a commercial 350-nm CMOS technology at cryogenic temperature. The programmability of the device offers a solution in the realization of a precise and flexible cryogenic system for qubits control in large-scale quantum computers. The device stores onto a floating-gate node a non-volatile charge, which can be bidirectionally modified by Fowler-Nordheim tunneling and impact-ionized hot electron injection. These two injection mechanisms are characterized and modeled in compact equations both at 300 K and 15 K. At cryogenic temperature, we show a fine-tuning of the stored charge compatible with the operation of a precise analog memory. Moreover, we developed accurate simulation models of the proposed floating-gate device that set the stage for designing a programmable analog circuit with better performances and accuracy at a few Kelvin. This work offers a solution in the design of configurable analog electronics to be employed for accurately read out the qubit state at deep-cryogenic temperature.

Fig: Simplified layout of the p-type floating-gate device under test. The capacitive coupling to the floating-gate node  is realized with the poly 2 control gate.

Acknowledgments: This work was supported by QUASIX Grant from  Italian Space Agency. This work was partially performed at Polifab, the  micro- and nanofabrication facility of Politecnico di Milano

[paper] Parameter Extraction Approaches for Memristor Models

Dmitry Alexeevich Zhevnenko^1,2, Fedor Pavlovich Meshchaninov^1,2, Vladislav Sergeevich Kozhevnikov^1,2, Evgeniy Sergeevich Shamin^1,2, Oleg Alexandrovich Telminov^1,2, and Evgeniy Sergeevich Gornev^1,2

Research and Development of Parameter Extraction Approaches for Memristor Models

Micromachines 2021, 12, 1220. 

DOI: 10.3390/mi12101220

   
1 Moscow Institute of Physics and Technology, Moscow, Russia;
2 JSС MERI, Zelenograd, Russia

Abstract: Memristors are among the most promising devices for building neural processors and non-volatile memory. One circuit design stage involves modeling, which includes the option of memristor models. The most common approach is the use of compact models, the accuracy of which is often determined by the accuracy of their parameter extraction from experiment results. In this paper, a review of existing extraction methods was performed and new parameter extraction algorithms for an adaptive compact model were proposed. The effectiveness of the developed methods was confirmed for the volt-ampere characteristic of a memristor with a vertical structure: TiN/HfxAl1-xOy/HfO2/TiN.

Fig: Model VACs with different numbers of inhomogeneities: 

(a) four inhomogeneities; (b) no inhomogeneities.

Acknowledgments: This research was funded by the Ministry of Science and Higher Education of the Russian  Federation, grant number 075-15-2020-791. Authors thank the Institute of Microelectronics Technology and High-Purity Materials RAS for access to experimental data on the study of graphene oxide memristor switching cycles.

[paper] Compact model of 3D NAND

Kul Lee and Hyungcheol Shin

Distinguishing capture cross section parameter between 

in GIDL erase compact model and TCAD

Japanese Journal of Applied Physics. 2021 Oct 14.

 
ISRC and School of Electrical Engineering and Computer Science, Seoul National University, (KR)
 

Abstract: Compact model of 3D NAND enables simulation at circuit- or system- level. Although compact model for gate-induced-drain-leakage(GIDL)-assisted erase has been proposed in previous study, it is difficult to be used practically because it has not been properly validated. In particular, capture-cross-section (CCS) value that is far from the real value is used. Also, it doesn’t consider the latest device structure and its operation. In this paper, conventional GIDL-assisted erase compact model is validated using TCAD and improved more practically. It is confirmed that CCS should be distinguished in TCAD and compact model due to their different definition in each of them. Based on their physical differences, equation that can interconvert them is proposed and the model is successfully validated with proper CCS. Finally, the advanced GIDL-assisted erase compact model considering tapered angle, single-side injection and word-line voltage is suggested.

Fig: Schematic cross section of 3D NAND string considering tapered angle. Double stacking and singe-side GIDL injection are assumed. It is assumed that the upper and lower stacks have the same dimension parameters.

[https://t.co/pmnr27KGAy] #Alibaba Announces #opensource #RISC-V-Based Xuantie Series #Processors #semi #chips #riscv https://t.co/VTIRXyYpEI

[https://t.co/pmnr27KGAy] #Alibaba Announces #opensource #RISC-V-Based Xuantie Series #Processors #semi #chips #riscv https://t.co/VTIRXyYpEI

— Wladek Grabinski (@wladek60) Oct 20, 2021

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from Twitter https://twitter.com/wladek60

October 20, 2021 at 01:36PM
via IFTTT

Apple Unveils New M1 Pro, Monster M1 Max SoCs

[https://t.co/rrssJ7q5A5] Apple Unveils New M1 Pro, Monster M1 Max SoCs #semiconductor #intel #apple #customsilicon #competition #leadership #semi https://t.co/9wsFqWvLXN

— Wladek Grabinski (@wladek60) Oct 19, 2021

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October 19, 2021 at 10:07AM
via IFTTT

President Macron wants #EU to double its #semi #production

Like Thierry Breton, the president Emmanuel Macron wants #EU to double its#semi  #production capacity. The #France and #Europe want to invest €6 billion and €40 billion respectively. [ @VIPress, #semiconductors, #chips] https://t.co/AzzG721WX9

— Wladek Grabinski (@wladek60) Oct 13, 2021

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October 13, 2021 at 01:38PM
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[paper] Parameter Extraction of Power MOSFET Models

Michihiro Shintani, Aoi Ueda and Takashi Sato

Accelerating Parameter Extraction of Power MOSFET Models Using Automatic Differentiation

IEEE Transactions on Power Electronics (2021)

DOI:  10.1109/TPEL.2021.3118057

 
Graduate School of Science and Technology, Nara Institute of Science and Technology, Ikoma (J)

Graduate School of Informatics, Kyoto University (J)
 

Abstract: The extraction of the model parameters is as im- portant as the development of compact model itself because simulation accuracy is fully determined by the accuracy of the pa- rameters used. This study proposes an efficient model-parameter extraction method for compact models of power MOSFETs. The proposed method employs automatic differentiation (AD), which is extensively used for training artificial neural networks. In the proposed AD-based parameter extraction, gradient of all the model parameters is analytically calculated by forming a graph that facilitates the backward propagation of errors. Based on the calculated gradient, computationally intensive numerical differentiation is eliminated and the model parameters are efficiently optimized. Experiments are conducted to fit current and capacitance characteristics of commercially available silicon carbide MOSFET using power MOSFET models having 13 model parameters. Results demonstrated that the proposed method could successfully derive the model parameters 3.50× faster than a conventional numerical-differentiation method while achieving the equal accuracy.

Fig: Backward propagation mode. The dashed arrows indicate the path from E to SCALE.

The propagated values on the path in the backward propagation are highlighted

Acknowledgment: This work was partially supported by JST-OPERA Program Grant Number JPMJOP1841, Japan. The part of this work is also supported by JSPS KAKENHI Grant 20H04156 and 20K21793.

[paper] MEMS Sensors Reliability

M. Hommel^a, H. Knab^a, S. Galal Yousef^b

Reliability of automotive and consumer MEMS sensors - An overview

Microelectronics Reliability (114252) online Oct. 11, 2021

DOI: 10.1016/j.microrel.2021.114252

a Robert-Bosch-GmbH, Automotive Electronics, Tübinger Str. 123, 72762 Reutlingen, Germany
b Bosch Sensortec GmbH, Gerhard-Kindler-Str. 9, 72770 Reutlingen, Germany

Abstract: In our daily life, sensors play more and a more important role. They take over many functions in the automotive world as well as in consumer products with an increasing dissemination of the internet of things. In addition, they offer a broad variety of new applications. Sensors are typically build up in a package including a sensing element (e.g. micromechanical structures in acceleration sensors or membranes in gas sensors, etc.) and a microelectronic chip to evaluate the sensor data. This article will give an overview, how the reliability of such a system is validated. The challenges for reliability in terms of requirements and qualification for automotive and consumer applications will be discussed. The complex structure of a sensor module in combination with a broad variety of materials implies many possible failure mechanisms, which have to be considered. Some relevant sensor failure mechanisms caused by mechanical shock, thermo-mechanical stress and the influence of humidity on sensor reliability will be shown. The challenges for describing the influence of humidity on the sensor lifetime by an acceleration model will be discussed in detail. Finally, the paper will give an outlook for the reliability challenges of future sensor applications.

Fig: Loads on a MEMS sensor module.

IEEE-EDS Santa Clara Valley/San Francisco Chapter October Seminar (Webex only)

Title: TCAD/SPICE-Augmented Machine Learning for Defect and Variation Study

Speaker: Dr. Hiu Yung Wong, San Jose State University

Friday, October 15, 2021 at noon – 1PM PDT

Register Here

Webex link will be distributed to the registrant via email.
Organizer contact: John Choi (wonhochoi at micron.com)

Abstract:

In semiconductor technology development, it is desirable to pinpoint the source of defect or variation through electrical measurements, which are non-destructive and have much higher throughput than the traditional failure analysis. This can be achieved through machine learning which is a powerful tool for correlating the electrical characteristics to the nature of the defect/variation. However, a good machine is only possible with enough well-controlled training data, which is difficult to obtain experimentally. TCAD and SPICE simulations which are well-calibrated to experimental data are proposed to generate the training data.

In this talk, we will first demonstrate the use of TCAD to generate data to train machines to deduce the epitaxial layer thickness of Si p-i-n diodes and the workfunction and operating temperature variation of Ga2O3 Schottky Barrier Diodes, based solely on the measured electrical characteristics. We will emphasize the use of minimal domain expertise to obviate the difficulties in feature extraction. We will also demonstrate the techniques that are important to make the TCAD-trained machine applicable to predicting experimental data. SPICE-augmented ML will be demonstrated for detecting contact resistance degradation in inverters. Finally, we will discuss the use of TCAD-augmented machines to help reverse engineering and understand novel devices.

Speaker Bio:

Hiu Yung Wong is an Assistant Professor in the EE department, San Jose State University. He received his Ph.D. degree in Electrical Engineering and Computer Science from the University of California, Berkeley in 2006. From 2006 to 2009, he worked as a Technology Integration Engineer in Spansion. From 2009 to 2018, he was a TCAD Senior Staff Application Engineer in Synopsys, during which he received the Synopsys Excellence Award in 2010. In 2021, he received the NSF CAREER award and the Newnan Brothers Award for Faculty Excellence.

His research interests include the applications of machine learning in simulation and manufacturing, cryogenic electronics, quantum computing, reliability simulations, wide bandgap devices (such as GaN, SiC, Ga2O3, and diamond) simulations, novel semiconductor devices design, and Design Technology Co-Optimization (DTCO). His work has produced 80 papers and 10 issued patents.

Call for Officer(s):

The Santa Clara Valley Chapter of the EDS is seeking candidates to apply for positions on the organizing executive committee for 2022. In particular we are looking for folks interested in becoming webmaster/communications director and secretary, although we welcome applications for treasurer, vice-chair, and chair as well. If you are interested in helping us organize technical talks and otherwise delivering value to EDS members in your local community, please email vijay_narasimhan@ieee.org, EDS SCV Chapter Chair, to express your interest.

More information at the IEEE EDS Santa Clara Valley-San Francisco Chapter Home Page

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[paper] WEAF Mnecosystem

J. Iannacci^1,2

The WEAF Mnecosystem: a perspective of MEMS/NEMS technologies

as pillars of future 6G, tactile internet and super-IoT

Microsystem Technologies, Oct. 5, 2021.

DOI:10.1007/s00542-021-05230-3

1 Center for Sensors and Devices (DS), FBK Trento, Italy
2 InnerBlender, Bologna, Italy

Abstract: The future 6G and tactile internet (TI) paradigms pose challenges and demand for requirements that are far beyond what the 5G—today at its dawn—will ever achieve. The classical approaches in designing devices, systems and infrastructures will not be suitable to build the AI-driven (Artificial Intelligence) 6G network. This work envisages a critical part for MEMS/NEMS technologies in making 6G turn into reality. Such a leading role sits on a reformulation of the common concept of Hardware (HW) triggered by Micro/Nanotechnologies and Materials. To this end, the WEAF Mnecosystem, i.e. the Water, Earth, Air and Fire Micro/Nanotechnologies Ecosystem, is conceived, leveraging the analogy with the four classical elements in nature, and is explained in details in the following pages, along with the discussion of some reference examples. In a nutshell, Earth and Air are the classical concepts of the Hardware (HW) and Software (SW), respectively. Water is the novel formulation of the concept of HW, which, like water, is liquid in terms of functional characteristics and gains, at the same time, some features typical of the SW (i.e. Air). Fire, eventually, is the HW devoted to harvest, store and transfer energy, raising its level of abstraction to the concept of heat, which flows from warmer to cooler bodies.

Fig: Schematic of the self-recovery design solution [i]: 

a.) Complete schematic of the RF-MEMS micro-relay; 

b.) schematic with the MEMS membrane made invisible 

in order to show the underlying micro-heater

Acknowledgements: The author wishes herewith to express his gratitude to Ms. Moira Osti for designing and realizing all the images included in this work. The author also wants to sincerely say thanks to Brando and Pietro, for accompanying the writing of parts of this work with their energy and unconditional serenity.

REF:

[i] Iannacci J, Repchankova A, Faes A, Tazzoli A, Meneghesso G, Niessner M (2010) Experimental investigation on the exploitation of an active mechanism to restore the operability of malfunctioning RF-MEMS switches. Proc Eng 5:734–737. DOI: /10.1016/j.proeng.2010.09.213

#Samsung #Foundry: #2nm Silicon in 2025

#Samsung #Foundry: #2nm Silicon in 2025

 

#semi #chip #manufacturing https://t.co/i57huVn0Kd

— Wladek Grabinski (@wladek60) Oct 7, 2021

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October 07, 2021 at 03:57PM
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[paper] Compact Schottky-barrier CNTFET Modeling

Manojkumar Annamalai and Michael Schroter

Compact formulation for the bias dependent quasi-static mobile charge in Schottky-barrier CNTFETs IEEE Transactions on Nanotechnology (2021)

DOI: 10.1109/TNANO.2021.3116694

CEDIC, Technische Universität Dresden (D)

Abstract: Carbon nanotube (CNT) field-effect transistors (FETs) are promising candidates for future high-frequency (HF) system-on-chip applications. Understanding and modeling mobile charge storage on CNTs is therefore essential for device optimization and circuit design. A physics-based compact analytical formulation is presented that enables an accurate approximation of the mobile charge in Schottky-barrier CNTFETs over the practically relevant bias range for HF circuit design. The formulation is C∞ continuous and yields accurate results also for the capacitances. The new formulation has been verified for both ballistic and scattering dominated carrier transport by employing device simulation, which was calibrated to experimental data from multi-tube CNTFETs.

Fig: Band diagram in a CNTFET along the axial direction (left red arrow) and, with applied gate bias, along the radial direction perpendicular to the gate (right blue arrow).

Acknowledgments: The authors would like to thank Dr. S. Mothes, formerly with CEDIC, for valuable discussions regarding the device simulator. This project was financially supported in part by the German National Science Foundation (DFG SCHR695/6-2).  

[paper] Gate Tunneling Current in MFIS NCFETs

Kshitiz Tyagi, Amit Verma, and Aloke K. Dutta

Modeling of the Gate Tunneling Current in MFIS NCFETs

IEEE Transactions on Electron Devices, pp. 1–8, Sept.18, 2021.

DOI: 10.1109/TED.2021.3114386

  

Department of Electrical Engineering, Indian Institute of Technology Kanpur, Kanpur 208016, India

  

Abstract: In this article, we present a model for the gate tunneling current (GTC) in metal-ferroelectric-insulator-semiconductor (MFIS) negative capacitance FETs (NCFETs), which, to the best of our knowledge, is the first such report. The model is numerical in nature, and is developed using the Tsu–Esaki formulation, employing the Wentzel–Kramer–Brillouin (WKB) approximation, in order to estimate the transmission coefficients of the carriers through the barriers. The ferroelectric (FE) material considered is HfO2, and is modeled using the Landau phase transition theory. Simulation results reveal a remarkable nonmonotonic dependence of the GTC on the FE layer thickness, an effect that we explain through the Landau model. Furthermore, it is shown how this GTC can be reduced by orders of magnitude without changing the overall dielectric capacitance-a feature that may prove to be beneficial in low-power circuit designs. Additionally, it is seen that the GTC is a weak function of the remanent polarization and coercive field of the FE. All the model predictions are validated through a comparison with the results obtained from 2-D TCAD simulations. The novel results presented in this work should serve as a guide for detailed experimental studies on the gate current characteristics of MFIS NCFETs.

Fig: Direct (DT) and Fowler–Nordheim (FN) tunneling modes of electrons having various energies, from the Si conduction band to the gate region

Acknowledgment: The authors would like to acknowledge the help of Mr. Amol Gaidhane at Nanolab, IIT Kanpur, in setting up the TCAD simulation workbench

[paper] Flexible Megahertz Organic Transistors

Jakob Leise^1,4, Jakob Pruefer^1,4, Ghader Darbandy¹, Aristeidis Nikolaou^1,4, Michele Giorgio², Mario Caironi², Ute Zschieschang³, Hagen Klauk³, Alexander Kloes¹, Benjamin Iñiguez⁴

and James W. Borchert⁵

Flexible megahertz organic transistors and the critical role of the device geometry on their dynamic performance

Journal of Applied Physics 130, 125501 (2021); 

DOI: 10.1063/5.0062146

  
1NanoP, TH Mittelhessen University of Applied Sciences, Gießen 35390, Germany
2Center for Nano Science and Technology @PoliMi, Istituto Italiano di Tecnologia, Milano 20133, Italy
3Max Planck Institute for Solid State Research, Stuttgart 70569, Germany
4DEEA, Uniersitat Rovira i Virgili, Tarragona 43007, Spain
5Georg August University of Goettingen, Goettingen 37077, Germany
  

Abstract: The development of organic thin-film transistors (TFTs) for high-frequency applications requires a detailed understanding of the intrinsic and extrinsic factors that influence their dynamic performance. This includes a wide range of properties, such as the device architecture, the contact resistance, parasitic capacitances, and intentional or unintentional asymmetries of the gate-to-contact overlaps. Here, we present a comprehensive analysis of the dynamic characteristics of the highest-performing flexible organic TFTs reported to date. For this purpose, we have developed the first compact model that provides a complete and accurate closed-form description of the frequency-dependent small-signal gain of organic field-effect transistors. The model properly accounts for all relevant secondary effects, such as the contact resistance, fringe capacitances, the subthreshold regime, charge traps, and non-quasistatic effects. We have analyzed the frequency behavior of low-voltage organic transistors fabricated in both coplanar and staggered device architectures on flexible plastic substrates. We show through S-parameter measurements that coplanar transistors yield more ideal small-signal characteristics with only a weak dependence on the overlap asymmetry. In contrast, the high-frequency behavior of staggered transistors suffers from a more pronounced dependence on the asymmetry. Using our advanced compact model, we elucidate the factors influencing the frequency-dependent small-signal gain and find that even though coplanar transistors have larger capacitances than staggered transistors, they benefit from substantially larger transconductances, which is the main reason for their superior dynamic performance.

Fig: Schematic cross-section of a top-contact (TC) organic TFT. Here, the semiconductor layer separates the source and drain contacts from the gate dielectric and thus from the gate-field-induced charge-carrier channel; hence, these transistors are also referred to as staggered TFTs. The overlap regions are assumed as a series connection of two capacitances. However, when the organic semiconductor (OSC) is operated in accumulation, the accumulation charges change the behavior of the series connection. The charge density at the source end of the channel is assumed to be found in the entire gate-to-source overlap region. 

Acknowledgments: The authors thankfully acknowledge funding for this project from the German Federal Ministry of Education and Research (“SOMOFLEX,” No. 13FH015IX6) and EU H2020 RISE (“DOMINO,” No. 645760), and the German Research Foundation (DFG) under Grant Nos. KL 1042/9-2, KL 2223/6-1, and KL 2223/6-2 (SPP FFlexCom). The authors would like

Memory for Synaptic Operations

Md. Hasan Raza Ansari, Udaya Mohanan Kannan and Seongjae Cho 

Core-Shell Dual-Gate Nanowire Charge-Trap Memory

for Synaptic Operations for Neuromorphic Applications

Nanomaterials 2021, 11, 1773

DOI 10.3390/nano11071773

 
Graduate School of IT Convergence Engineering, Gachon University, Seongnam 13120, Korea;
 

Abstract: This work showcases the physical insights of a core-shell dual-gate (CSDG) nanowire transistor as an artificial synaptic device with short/long-term potentiation and long-term depression (LTD) operation. Short-term potentiation (STP) is a temporary potentiation of a neural network, and it can be transformed into long-term potentiation (LTP) through repetitive stimulus. In this work, floating body effects and charge trapping are utilized to show the transition from STP to LTP while de-trapping the holes from the nitride layer shows the LTD operation. Furthermore, linearity and symmetry in conductance are achieved through optimal device design and biases. In a system-level simulation, with CSDG nanowire transistor a recognition accuracy of up to 92.28% is obtained in the Modified National Institute of Standards and Technology (MNIST) pattern recognition task. Complementary metal-oxide-semiconductor (CMOS) compatibility and high recognition accuracy makes the CSDG nanowire transistor a promising candidate for the implementation of neuromorphic hardware.

Fig: Schematic representation of biological synapse and 2D representation of CSDG nanowire transistor for artificial synapse device.

Acknowledgement: This research was supported by the National Research Foundation of Korea (NRF) funded by the Ministry of Science and ICT (MSIT) (No. 2016M3A7B4910348, Nano-Material Technology Development Program, 50%) and was partly supported by Institute of Information & Communications Technology Planning & Evaluation (IITP) grant funded by the Korean government (MSIT) (No. 2020-0-01294, Development of IoT based edge computing ultra-low power artificial intelligent processor, 50%).

[see also] M. H. R. Ansari, S. Cho, J.-H. Lee, and B.-G. Park, “Core-Shell Dual-Gate Nanowire Memory as a Synaptic Device for Neuromorphic Application,” IEEE Journal of the Electron Devices Society, pp. 1–1, 2021. DOI: 10.1109/JEDS.2021.3111343

[paper] Organic Semiconductor Devices

D. Oussalah^1,2, R. Clerc², J. Baylet¹, R. Paquet¹, C. Sésé¹, C. Laugier¹, B. Racine¹

and J. Vaillant¹

On the minimum thickness of doped electron/hole transport layers 

in organic semiconductor devices 

Journal of Applied Physics 130, 125502 (2021);

DOI: 10.1063/5.0060429

  
1Université Grenoble Alpes, CEA, Leti, Grenoble 38000, France
2Université de Lyon, UJM-Saint-Etienne, CNRS, IOGS, Lab. Hubert Curien, UMR5516 St-Etienne, France

  

Abstract: Doped hole (respectively electron) transport layers [HTLs (respectively ETLs)] are commonly used in evaporated organic devices to achieve high work function hole contact (respectively low work function electron contact) in organic LEDs to inject large current, in solar cells to increase the open circuit voltage, and in photodetectors to minimize the dark current. However, optimization of the HTL thickness results from a delicate trade-off. Indeed, on the one hand, to minimize the impact of HTLs on light propagation and series resistance effects, it is commonly admitted that HTLs must be kept as thin as possible. In this work, a model, validated by drift and diffusion simulations, has shown that, depending of the doping level, a minimum thickness between 10 and 20 nm was needed to prevent the transport layer work function from degradation due to field effects. Experiments have been performed on template p-only devices featuring a single HTL of various thicknesses and doping, confirming the validity of the model. Finally, simulations have been performed on a p-i-n device featuring both HTL and ETL. These results constitute precious indications for the design of efficient evaporated organic LEDs, solar cells, or photodetectors.

Fig: Image of a top view of the 200 mm silicon wafer processed to realize TiN/STTB:F4TCNQ/ZnPc:C60/Ag devices.

[paper] Enhancing multi-functionality of reconfigurable transistors

Y.V. Bhuvaneshwari and Abhinav Kranti

Enhancing multi-functionality of reconfigurable transistors 

by implementing high retention capacitorless dynamic memory

Semicond. Sci. Technol. 36 (2021) 115003 (9pp)

DOI:10.1088/1361-6641/ac2315

Low Power Nanoelectronics Research Group, Department of Electrical Engineering, Indian Institute of Technology Indore, Simrol, Indore 453552, Madhya Pradesh, India

Abstract: A key indicator of multi-functional attributes of a transistor is technological competitiveness vis-a-vis existing architectures. Apart from the well-known logic circuit implementation through reconfigurable field effect transistors (RFETs), this work showcases feasible memory operation by realising capacitorless (1T) dynamic random access memory (DRAM). The memory operation in RFET is achieved through back control gate which creates an electrostatic potential well to store holes. Due to the inherent features of RFET architecture a wider and deeper potential well results in a significantly high retention time (RT) of 2.3s at 85C for a total length of 90 nm. Apart from high retention, RFET based 1T-DRAM exhibits a low write time of ∼2ns, sense margin (SM) of ∼76µA/µm and a high current ratio (CR) of ∼105. Benchmarking the performance metrics against previously published results indicates competitiveness for RT in terms of total length, storage volume and high temperature operation. Critical insights aiding competitive multi-functional behaviour through 1T-DRAM highlights the possible implementation of logic and memory blocks with RFETs.

Fig: Schematic diagram of a planar DG RFET with two PGs and one CG. The CG length (Lcg) and PG length (Lpg) were varied from 100 to 10 nm, spacing (Lgap) between CG and PG was varied from 40 to 30 nm, and the undoped film of thickness (Tsi) was varied from 9 to 12 nm. The thickness of HfO2 layer (THfO2) was kept constant at 4 nm. A midgap workfunction (φm=4.7 eV) was used for polarity and CGs. Holes are stored at the back surface (y=Tsi) in the potential well created due to the application of a negative voltage at the back CG.

Acknowledgments: This work was supported by the Science and Engineering Research Board (SERB), Department of Science and Technology (DST), Government of India, under GrantCRG/2019/002937.

[@iannak1] The size of the investment needed for one single new state-of-art fab is way beyond the Semiconductor Industry support plans of all European governments #semi #fab #chip #wafer #investment #EU https://t.co/aj6fnXB4r8

[@iannak1] The size of the investment needed for one single new state-of-art fab is way beyond the Semiconductor Industry support plans of all European governments #semi #fab #chip #wafer #investment #EU https://t.co/aj6fnXB4r8

— Wladek Grabinski (@wladek60) Oct 1, 2021

---

from Twitter https://twitter.com/wladek60

October 01, 2021 at 08:55AM
via IFTTT

[SEMI Press Release] SEMI Applauds European Chips Act, Aimed at Boosting Semiconductor R&D and Manufacturing https://t.co/WZOd8Sw5Sh #Europe #research #development #semiconductors #manufacturing #publicpolicy #semi #chip #EU https://t.co/mHGUZkRaXY

[SEMI Press Release] SEMI Applauds European Chips Act, Aimed at Boosting Semiconductor R&D and Manufacturing https://t.co/WZOd8Sw5Sh #Europe #research #development #semiconductors  #manufacturing #publicpolicy #semi #chip #EU https://t.co/mHGUZkRaXY

— Wladek Grabinski (@wladek60) Sep 30, 2021

---

from Twitter https://twitter.com/wladek60

September 30, 2021 at 08:31PM
via IFTTT

[paper] New Design Concept for the IoT Era

Pedro Toledo, Graduate Student Member, IEEE, Roberto Rubino, Graduate Student Member, IEEE, Francesco Musolino, Member, IEEE, and Paolo Crovetti, Senior Member, IEEE

Re-Thinking Analog Integrated Circuits in Digital Terms: A New Design Concept for the IoT Era

IEEE Transactions on Circuits and Systems—II: Express Briefs, 

Vol. 68, No. 3, March 2021

DOI:  10.1109/TCSII.2021.3049680

* DET, Politecnico di Torino (IT)

Abstract: A steady trend towards the design of mostly-digital and digital-friendly analog circuits, suitable to integration in mainstream nanoscale CMOS by a highly automated design flow, has been observed in the last years to address the requirements of the emerging Internet of Things (IoT) applications. In this context, this tutorial brief presents an overview of concepts and design methodologies that emerged in the last decade, aimed to the implementation of analog circuits like Operational Transconductance Amplifiers, Voltage References and Data Converters by digital circuits. The current design challenges and application scenarios as well as the future perspectives and opportunities in the field of digital-based analog processing are finally discussed.

Fig: a) Kuijk’s Bandgap voltage reference [i]. b) Microcontroller-based proof

of concept prototype.

REF:

[i] K. E. Kuijk, “A precision reference voltage source,” IEEE J. Solid-StateCircuits, vol. SSC-8, no. 3, pp. 222–226, Jun. 1973.

[book] MEMS Product Development

Fitzgerald, Alissa M., Chung, Charles C.

MEMS Product Development: From Concept to Commercialization

ISBN 978-3-030-61709-7

Drawing on their experiences in successfully executing hundreds of MEMS development projects, the authors present the first practical guide to navigating the technical and business challenges of MEMS product development, from the initial concept stage all the way to commercialization. The strategies and tactics presented, when practiced diligently, can shorten development timelines, help avoid common pitfalls, and improve the odds of success, especially when resources are limited. MEMS Product Development illuminates what it really takes to develop a novel MEMS product so that innovators, designers, entrepreneurs, product managers, investors, and executives may properly prepare their companies to succeed.

Table of contents (20 chapters)

1. The Opportunities and Challenges of MEMS Product Development, pp. 3-8
2. Economics of Semiconductor Device Manufacturing and Impacts on MEMS Product Development, pp. 9-16
3. Stages of MEMS Product Development, pp. 17-28
4. What Is the Product? Requirements Analysis, pp. 31-45
5. Is There a Business Opportunity? Product Unit Cost Modeling, pp. 47-57
6. What Is the Budget for Development?, pp. 59-70
7. Leveraging Third-Party Intellectual Property to Accelerate Product Development, pp. 71-79
8. Organization Planning for Successful Development, pp. 81-92
9. The MEMS Product: Functional Partitioning and Integration, pp. 95-110
10. Starting a New MEMS Device Design, pp. 111-127
11. Design for Manufacturing: Process Integration and Photomask Layout, pp. 129-148
12. Design for Back-end-of-Line Processes, pp. 149-156
13. Strategies for Codevelopment of the Electronics and Package, pp. 157-166
14. Planning a Development Test Program, pp. 167-183
15. Risk Mitigation Strategies for Prototype Fabrication, pp. 185-195
16. Documenting MEMS Product Technology for Transfer to Manufacturing, pp. 197-211
17. Determining Readiness for Volume Production, pp. 215-222
18. Selecting a Foundry Partner, pp. 223-239
19. Transferring Technology for Production, pp. 241-252
20. Manufacturing Test: Opportunity, Cost, and Managing Risk, pp. 253-268

[mos-ak] [online publications] 18th MOS-AK ESSDERC/ESSCIRC Workshop Grenoble; Sept. 6, 2021

The MOS-AK Association with local technical program promoters and the International MOS-AK Board of R&D Advisers as well as all the Extended MOS-AK TPC Committee have organized its subsequent 18th MOS-AK ESSDERC/ESSCIRC Workshop as a virtual/online event on Sept.6, 2021

Online Publications:

There are MOS-AK technical presentations covering selected aspects of the compact/SPICE modeling and its Verilog-A standardization; see all the slide presentations online at corresponding link:

https://www.mos-ak.org/grenoble_2021/

The MOS-AK Association plans to continue its standardization efforts by organizing future compact modeling meetings, workshops and courses around the globe later this year and thru the next 2022 year, including:

• 14th US MOS-AK Workshop, Silicon Valley (US) Dec. 2021
  
• in timeframe of IEDM and Q4 CMC Meetings
• 4th MOS-AK at LAEDC Workshop, Mexico 2022

W.Grabinski on the behalf of International MOS-AK Committee

WG29092021

 

[paper] Degradations in LDMOS Transistors

Yen-Pu Chen¹, Bikram K. Mahajan¹, Dhanoop Varghese², Srikanth Krishnan², Vijay Reddy²

and Muhammad A. Alam¹

Three-point I–V spectroscopy deconvolves region-specific degradations in LDMOS transistors

Appl. Phys. Lett. 119, 122102 (2021); 

DOI: 10.1063/5.0058477

1 Department of ECE, Purdue University, West Lafayette, Indiana 47906, USA
2 Texas Instruments Inc., Dallas, Texas 75043, USA

Abstract: Unlike traditional logic transistors, hot carrier degradation (HCD) in power transistors involves simultaneous and potentially correlated degradation in multiple regions. One must deconvolve and characterize the voltage- and temperature-dependence of these region-specific degradations to develop a predictive HCD model of power transistors. Unfortunately, power transistors' doping and geometrical complexities make it challenging to use traditional defect-profiling techniques, such as charge-pumping or gated-diode methods. This Letter uses a physics-based tandem-FET model of Laterally Diffused MOS (LDMOS) transistors to develop a “three-point I–V spectroscopy” technique that uses the time-evolution of three critical points of the measured I–V characteristics to extract mobility and threshold voltage degradations in the channel and drift regions. This innovative approach should generalize to other configurations of the LDMOS transistor as well.

Fig: The proposed tandem-FET compact model. The channel (ch) and the drift (dr) regions function individually as a MOSFET with different 𝑉th and dimensions. Three adjustable degradation parameters are 𝛥𝜇𝑐ℎ, 𝛥𝑉𝑐ℎth, and 𝛥𝜇𝑑𝑟.

Acknowledgements: Y.-P.C and B.K.M contributed equally to this work. The authors gratefully acknowledge the access to the characterization facilities at Birck Nanotechnology Center, Purdue University, for the results presented in this article.

[Now Open for Submission] IEEE Journal on Flexible Electronics

The IEEE Journal on Flexible Electronics (J-FLEX) publishes cutting edge research covering all aspects of sensors, transistors, related devices, circuits, systems on flexible, disposable, stretchable and degradable substrates. This includes various functional and sustainable materials, material-integrated sensing, interface subsystems, corresponding actuators, energy harvesting, energy storage devices, modelling, simulation, manufacturing, integration or packaging in soft and flexible substrates and all applications of flexible electronics. Topics such as 3D printed or heterogenous integration, use of sustainable materials and processes aligned with circular economy are also in the scope of this journal.     Submit your article today, and get published in the IEEE Journal on Flexible Electronics.     Best regards, Ravinder Dahiya Editor-in-Chief, IEEE Journal on Flexible Electronics     If you have an IEEE Account, manage your IEEE communications preferences here. Users without an IEEE Account can access the Privacy Portal to view selected preferences and policies.       © 2021 IEEE– All rights reserved.   Website |  Privacy Policy |  Contact