[Short Course] MACHINE LEARNING FOR ELECTRON DEVICES

Short Course on

MACHINE LEARNING FOR ELECTRON DEVICES

3-6 October 2023, IIT Roorkee

Four day residential program to learn and explore the role of Machine Learning in shaping the future of the semiconductor EDA.

KEY HIGHLIGHTS

• Lectures from basic machine learning to advanced ideas
• Hands-on tutorials for developing your own Machine learning models
• Excellent networking opportunity
• Interaction with experts from industry and academia
• UG Fellowships up to ₹ 10000/month for selected participants
• Funding opportunity upto INR 40Lacs as start-up seed grant for selected ideas

EVENT SCHEDULE <http://ece.iitr.ac.in/diraclab/mled23/>

[Special Issue] ACM Transactions on Machine Learning for CAD / EDA

ACM Transactions on Design Automation of Electronic Systems

Special Issue on Machine Learning for CAD / EDA 

Guest Editors: 

• Yibo Lin, Peking University

• Avi Ziv, IBM Research, Haifa, Israel

• Haoxing Ren, NVIDIA Corp.

Advances in Machine Learning (ML) over the past half-dozen years have revolutionized the effectiveness of ML for a variety of applications. However, design processes present challenges that require parallel advances in ML and CAD as compared to traditional ML applications such as image classification. 

This special issue seeks original submission on ML applications to the entire design flow - including ML applications to validation and test. The application of machine learning to mask preparation and layout generation are topics which are seeing very active research recently. ML is also being applied to improve the robustness of integrated circuits and systems. Power and thermal management are probably the most important limiting factors for ICs today - ML-based techniques are being explored to address this bottleneck. All these topics, as well as further potential topics mentioned below, are of interest to this special issue. In addition to submissions from academia, submissions from industry are much welcome. 

Topics of interest to this special issue include, but not limited to, the following:

• ML for system-level design

• ML approaches to logic design and synthesis

• ML for timing

• ML for clock networks and power grids

• ML for variation-aware design, analysis and optimization

• ML for physical design

• ML for analog design

• ML for power and thermal management

• ML for Design Technology Co-Optimization (DTCO)

• ML methods to predict aging and reliability

• Labeled and unlabeled data in ML for CAD

• ML techniques for resource management in many cores

• ML for verification and validation

• ML for test

• ML for library design and optimization 

Important Dates:

• Submissions deadline: February 15, 2022

• First-round review decisions: April 15, 2022

• Deadline for revision submissions: May 15, 2022

• Notification of final decisions: June 15, 2022

• Tentative publication: Summer 2022 

Submission Information: 

Authors are encouraged to submit high-quality original research contributions. Please clearly identify the additional material from any original conference or workshop paper in your submitted manuscript. Submissions should be made through the ACM TODAES submission site (http://mc.manuscriptcentral.com/todaes) and formatted according to TODAES author guidelines at: https://dl.acm.org/journal/todaes/author-guidelines. Select the paper type “Special Issue on Machine Learning for CAD/EDA.” 

For questions and further information, please contact guest editors at:

• Yibo Lin

• Avi Ziv

• Haoxing Ren

[paper] Parameter Extraction Approaches for Memristor Models

Dmitry Alexeevich Zhevnenko^1,2, Fedor Pavlovich Meshchaninov^1,2, Vladislav Sergeevich Kozhevnikov^1,2, Evgeniy Sergeevich Shamin^1,2, Oleg Alexandrovich Telminov^1,2, and Evgeniy Sergeevich Gornev^1,2

Research and Development of Parameter Extraction Approaches for Memristor Models

Micromachines 2021, 12, 1220. 

DOI: 10.3390/mi12101220

   
1 Moscow Institute of Physics and Technology, Moscow, Russia;
2 JSС MERI, Zelenograd, Russia

Abstract: Memristors are among the most promising devices for building neural processors and non-volatile memory. One circuit design stage involves modeling, which includes the option of memristor models. The most common approach is the use of compact models, the accuracy of which is often determined by the accuracy of their parameter extraction from experiment results. In this paper, a review of existing extraction methods was performed and new parameter extraction algorithms for an adaptive compact model were proposed. The effectiveness of the developed methods was confirmed for the volt-ampere characteristic of a memristor with a vertical structure: TiN/HfxAl1-xOy/HfO2/TiN.

Fig: Model VACs with different numbers of inhomogeneities: 

(a) four inhomogeneities; (b) no inhomogeneities.

Acknowledgments: This research was funded by the Ministry of Science and Higher Education of the Russian  Federation, grant number 075-15-2020-791. Authors thank the Institute of Microelectronics Technology and High-Purity Materials RAS for access to experimental data on the study of graphene oxide memristor switching cycles.

[paper] ML based Aging-Aware FPGA Framework

Behnam Ghavami, Milad Ibrahimipour, Zhenman Fang, Lesley Shannon 

MAPLE: A Machine Learning based Aging-Aware FPGA Architecture Exploration Framework

31st International Conference on Field-Programmable Logic and Applications

(FPL 2021 Short Paper),

Virtual Conference, Sept 2021

*Simon Fraser University, Burnaby, BC, Canada

Abstract: In this paper, we develop a framework called MAPLE to enable the aging-aware FPGA architecture exploration. The core idea is to efficiently model the aging-induced delay degradation at the coarse-grained FPGA basic block level using deep neural networks (DNNs). For each type of the FPGA basic block such as LUT and DSP, we first characterize its accurate delay degradation via transistor-level SPICE simulation under a versatile set of aging factors from the FPGA fabric and in-field operation. Then we train one DNN model for each block type to quickly and accurately predict the complex relation between its delay degradation and comprehensive aging factors. Moreover, we integrate our DNN models into the widely used Verilog-to-Routing toolflow (VTR 8) to support analyzing the impact of aging-induced delay degradation on the entire large scale FPGA architecture. Experimental results demonstrate that MAPLE can predict the delay degradation of FPGA blocks 104 to 107 times faster than transistor-level SPICE simulation, with a prediction error less than 0.7%. Our case study demonstrates that FPGA architects can effectively leverage MAPLE to explore better aging-aware FPGA architectures.

Fig: Overview of FPGA fabric and in-field factors affecting FPGA aging at transistor and basic block levels. We use DNNs to model FPGA delay degradation at basic block level.

Acknowledgements: We acknowledge the support from Government of Canada Technology Demonstration Program and MDA Systems Ltd; NSERC Discovery Grant RGPIN-2019-04613 and DGECR 2019-00120; Canada Foundation for Innovation John R. Evans Leaders Fund; Simon Fraser University New Faculty Start-up Grant; Xilinx, Huawei and Nvidia.

[papers] Aging and Device Reliability Compact Modeling

IEEE International Reliability Physics Symposium

(IRPS 2021)

[1] N. Chatterjee, J. Ortega, I. Meric, P. Xiao and I. Tsameret, "Machine Learning On Transistor Aging Data: Test Time Reduction and Modeling for Novel Devices," 2021 IEEE International Reliability Physics Symposium (IRPS), 2021, pp. 1-9, doi: 10.1109/IRPS46558.2021.9405188.

Abstract: Accurately modeling the I-V characteristics and current degradation for transistors is central to predicting circuit end-of-life behavior. In this work, we propose a machine learning model to accurately model current degradation at various stress conditions and extend that to make nominal use-bias predictions. The model can be extended to track and predict any parametric change. We show an excellent agreement of the model with experimental results. Furthermore, we use a deep neural network to model the I-V characteristics of aged transistors over a wide drain and gate playback bias range and show an excellent agreement with experimental results. We show that the model is reliably able to interpolate and extrapolate demonstrating that it learns the underlying functional form of the data.

URL: https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=9405188&isnumber=9405088

[2] P. B. Vyas et al., "Reliability-Conscious MOSFET Compact Modeling with Focus on the Defect-Screening Effect of Hot-Carrier Injection," 2021 IEEE International Reliability Physics Symposium (IRPS), 2021, pp. 1-4, doi: 10.1109/IRPS46558.2021.9405197.

Abstract: Accurate prediction of device aging plays a vital role in the circuit design of advanced-node CMOS technologies. In particular, hot-carrier induced aging is so complicated that its modeling is often significantly simplified, with focus limited to digital circuits. We present here a novel reliability-aware compact modeling method that can accurately capture the full post-stress I-V characteristics of the MOSFET, taking into account the impact of drain depletion region on induced defects.

URL: https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=9405197&isnumber=9405088

[3] Z. Wu et al., "Physics-based device aging modelling framework for accurate circuit reliability assessment," 2021 IEEE International Reliability Physics Symposium (IRPS), 2021, pp. 1-6, doi: 10.1109/IRPS46558.2021.9405106.

Abstract: An analytical device aging modelling framework, ranging from microscopic degradation physics up to the aged I-V characteristics, is demonstrated. We first expand our reliability oriented I-V compact model, now including temperature and body-bias effects; second, we propose an analytical solution for channel carrier profiling which-compared to our previous work-circumvents the need of TCAD aid; third, through Poisson's equation, we convert the extracted carrier density profile into channel lateral and oxide electric fields; fourth, we represent the device as an equivalent ballistic MOSFETs chain to enable channel “slicing” and propagate local degradation into the aged I-V characteristics, without requiring computationally-intensive self-consistent calculations. The local degradation in each channel “slice” is calculated with physics-based reliability models (2-state NMP, SVE/MVE). The demonstrated aging modelling framework is verified against TCAD and validated across a broad range of VG/VD/T stress conditions in a scaled finFET technology.

URL: https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=9405106&isnumber=9405088

[CAS Seasonal School] How Technology is Impacting Agribusiness

How Technology is Impacting Agribusiness

A CAS seasonal school on technology and agribusiness will be held virtually from November 16th to November 20th. The program is quite interesting and we invite you to register through our web page www.asic-chile.cl. Registration is free.

The current world population of 7.6 billion is expected to reach 9.8 billion in 2050. According to the United Nations Food and Agriculture Organization (FAO) global agricultural productivity must increase by 50% – 70% to be able to feed the world population in 2050. Other researchers consider that reducing the waste of food would be enough.

Factors if not obstacles to be considered to meet global food demand by 2050 and beyond:

• Less arable land: As cities are growing, the space allowed to agriculture is shrinking.
• Climate change: Impacting dramatically agribusiness.
• Role of the agribusiness on the GHG emissions.
• Planet boundaries and the role of agribusiness.
• Availability of freshwater.
• Soil degradation.

The need has never been greater for innovative and sustainable solutions and technology should lead to significant improvement in our food and nutritional security.

In this seasonal school prestigious researchers and experts from all over the world will present the problems and challenges agribusiness is facing and how technologies such as IoT, AI, Machine Learning, sensors, electronic circuits, electronic systems, ICs, etc., can be applied to improve and solve the majority of those problems.

This is the first of a series of “Technology and Agribusiness” Seasonal Schools. It will be a meeting point for professionals working on Precision and Smart Agriculture, as well as professionals working on IoT, sensors, electronic circuits, electronic systems, ICs, etc.

We invite you to participate in this first version of the Technology and Agribusiness Seasonal School, which due to the pandemic will be 100% online and free of charge.

Join us!

[paper] TCAD-Machine Learning Framework

Hiu Yung Wong¹ (Senior Member, IEEE), Ming Xiao², Boyan Wang², Yan Ka Chiu¹, Xiaodong Yan³, Jiahui Ma³, Kohei Sasaki⁴, Han Wang³ (Senior Member, IEEE)

and Yuhao Zhang² (Member, IEEE)

TCAD-Machine Learning Framework for Device Variation and Operating Temperature Analysis with Experimental Demonstration

IEEE J-EDS, vol. 8, pp. 992-1000, 2020

doi: 10.1109/JEDS.2020.3024669.

¹Department of Electrical Engineering, San Jose State University, San Jose, CA 95112, USA
²Virginia Polytechnic Institute, State University, Blacksburg, VA 24060, USA
³Ming Hsieh Department of Electrical Engineering, University of Southern California, Los Angeles, CA 90089, USA
⁴Development Department, Novel Crystal Technology Inc., Sayama 3501328, Japan

Abstract: This work, for the first time, experimentally demonstrates a TCAD-Machine Learning (TCADML) framework to assist the analysis of device-to-device variation and operating (ambient) temperature without the need of physical quantities extraction. The ML algorithm used in this work is the Principal Component Analysis (PCA) followed by third order polynomial regression. After calibrated to limited ‘expensive’ experimental data, ‘low cost’ TCAD simulation is used to generate a large amount of device data to train the ML model. The ML was then used to identify the root cause of device variation and operating temperature from any given experimental current-voltage (I-V) characteristics. We applied this framework to study the ultra-wide-bandgap gallium oxide (Ga2O3) Schottky barrier diode (SBD), an emerging device technology that holds great promise for temperature sensing, RF, and power applications in harsh environments. After calibration, over 150,000 electrothermal TCAD simulations are performed with random variation of physical parameters (anode effective work function, drift layer doping, and drift layer thickness) and operating temperature. An ML model is trained using these TCAD data and we found 1,000-10,000 TCAD data can train an accurate machine. We show that without physical quantities extraction, performing PCA is essential for the TCAD trained ML model to be applicable to analyze experimental characteristics. The physical parameters and temperatures predicted by the ML model show good agreement with experimental analysis. Our TCAD-ML framework shows great promise to accelerate the development of new device technologies with a significantly more efficient process of material and device experimentation.

FIG: Flow chart diagram of the proposed TCAD-Machine Learning framework. All components are demonstrated in this article except the MLDatabase which stores previously trained ML algorithms.

Acknowledgment: The authors thank Dr. Pooya Jannaty of Cruise and Dr. Philip Leong of the University of Sydney for the discussion of ML algorithms. The experimental work is in part supported by the Southeastern Center for Electrical Engineering Education program and the High Density Integration industry mini-consortium of the Center for Power Electronics Systems at Virginia Tech.