Y.V. Bhuvaneshwari and Abhinav Kranti
Enhancing multi-functionality of reconfigurable transistors
by implementing high retention capacitorless dynamic memory
Semicond. Sci. Technol. 36 (2021) 115003 (9pp)
DOI:10.1088/1361-6641/ac2315
Low Power Nanoelectronics Research Group, Department of Electrical Engineering, Indian Institute of Technology Indore, Simrol, Indore 453552, Madhya Pradesh, India
Abstract: A key indicator of multi-functional attributes of a transistor is technological competitiveness vis-a-vis existing architectures. Apart from the well-known logic circuit implementation through reconfigurable field effect transistors (RFETs), this work showcases feasible memory operation by realising capacitorless (1T) dynamic random access memory (DRAM). The memory operation in RFET is achieved through back control gate which creates an electrostatic potential well to store holes. Due to the inherent features of RFET architecture a wider and deeper potential well results in a significantly high retention time (RT) of 2.3s at 85C for a total length of 90 nm. Apart from high retention, RFET based 1T-DRAM exhibits a low write time of ∼2ns, sense margin (SM) of ∼76µA/µm and a high current ratio (CR) of ∼105. Benchmarking the performance metrics against previously published results indicates competitiveness for RT in terms of total length, storage volume and high temperature operation. Critical insights aiding competitive multi-functional behaviour through 1T-DRAM highlights the possible implementation of logic and memory blocks with RFETs.
Fig: Schematic diagram of a planar DG RFET with two PGs and one CG. The CG length (Lcg) and PG length (Lpg) were varied from 100 to 10 nm, spacing (Lgap) between CG and PG was varied from 40 to 30 nm, and the undoped film of thickness (Tsi) was varied from 9 to 12 nm. The thickness of HfO2 layer (THfO2) was kept constant at 4 nm. A midgap workfunction (φm=4.7 eV) was used for polarity and CGs. Holes are stored at the back surface (y=Tsi) in the potential well created due to the application of a negative voltage at the back CG.
Acknowledgments: This work was supported by the Science and Engineering Research Board (SERB), Department of Science and Technology (DST), Government of India, under GrantCRG/2019/002937.
