Showing posts with label pattern recognition. Show all posts
Showing posts with label pattern recognition. Show all posts

Oct 4, 2021

Memory for Synaptic Operations

Md. Hasan Raza Ansari, Udaya Mohanan Kannan and Seongjae Cho 
Core-Shell Dual-Gate Nanowire Charge-Trap Memory
for Synaptic Operations for Neuromorphic Applications
Nanomaterials 2021, 11, 1773
DOI 10.3390/nano11071773
 
Graduate School of IT Convergence Engineering, Gachon University, Seongnam 13120, Korea;
 
Abstract: This work showcases the physical insights of a core-shell dual-gate (CSDG) nanowire transistor as an artificial synaptic device with short/long-term potentiation and long-term depression (LTD) operation. Short-term potentiation (STP) is a temporary potentiation of a neural network, and it can be transformed into long-term potentiation (LTP) through repetitive stimulus. In this work, floating body effects and charge trapping are utilized to show the transition from STP to LTP while de-trapping the holes from the nitride layer shows the LTD operation. Furthermore, linearity and symmetry in conductance are achieved through optimal device design and biases. In a system-level simulation, with CSDG nanowire transistor a recognition accuracy of up to 92.28% is obtained in the Modified National Institute of Standards and Technology (MNIST) pattern recognition task. Complementary metal-oxide-semiconductor (CMOS) compatibility and high recognition accuracy makes the CSDG nanowire transistor a promising candidate for the implementation of neuromorphic hardware.
Fig: Schematic representation of biological synapse and 2D representation of CSDG nanowire transistor for artificial synapse device.

Acknowledgement: This research was supported by the National Research Foundation of Korea (NRF) funded by the Ministry of Science and ICT (MSIT) (No. 2016M3A7B4910348, Nano-Material Technology Development Program, 50%) and was partly supported by Institute of Information & Communications Technology Planning & Evaluation (IITP) grant funded by the Korean government (MSIT) (No. 2020-0-01294, Development of IoT based edge computing ultra-low power artificial intelligent processor, 50%).

[see also] M. H. R. Ansari, S. Cho, J.-H. Lee, and B.-G. Park, “Core-Shell Dual-Gate Nanowire Memory as a Synaptic Device for Neuromorphic Application,” IEEE Journal of the Electron Devices Society, pp. 1–1, 2021. DOI: 10.1109/JEDS.2021.3111343