[paper] Cryo FD SOI LNA Design

Giovani Britton, Salvador Mir, Estelle Lauga-Larroze, Benjamin Dormieu, Jose Lugo, Joao Azevedo, Sebastien Sadlo, Quentin Berlingard, Mikael Casse, Philippe Galy

Using DC transistor characterization measurements for LNA design at cryogenic temperatures

(2026) researchsquare.com

DOI: 10.21203/rs.3.rs-7754596/v1

1. STMicroelectronics, Crolles (F)
2. Univ. Grenoble Alpes, CNRS, Grenoble-INP, TIMA, Grenoble (F)
3. Univ. Grenoble Alpes, CEA-Leti, Grenoble (F)
4. Univ. Grenoble Alpes, CNRS, Grenoble-INP, IMEP-LAHC, Grenoble (F)

Abstract: The design of Radio Frequency (RF) cryogenic circuits has attracted much interest in recent years due to applications such as quantum computers. Interface electronics with ultra-low levels of power consumption at temperatures as low as 4 K are required. Silicon technologies are being considered for implementation because of the possibility of large-scale qubit integration with energy-efficient readout and control interfaces. However, the design of RF cryogenic circuits is complicated because of the lack of standard design kits with the corresponding component models for their simulation at these temperatures. Alternative approaches to avoid costly design and fabrication cycles are possible, in particular the use of Look-Up-Table (LUT) based techniques that exploit characterization data of circuit components at cryogenic temperature. In this paper, we make use of this approach for the design of a RF Low Noise Amplifier (LNA) using a 28 nm FD-SOI technology that has been characterized at cryogenic temperatures1using DC measurements. Furthermore, we also experimentally demonstrate that the DC measurements used are valid to extract the transistor noise parameters used in the LUT-based analysis.

Fig: Measurement of: (a) transconductance gm, and (b) threshold voltage Vth 

for the 28nm FD-SOI technology, from 300K down to 4K.

Acknowledgements: This work was supported by the French CIFRE program and the Labex MINOS of French program ANR-10-LABX-55-01.

[paper] Noise modeling for cryogenic applications

Giovani Britton^1,2, Salvador Mir², Estelle Lauga-Larroze², Benjamin Dormieu¹, Quentin Berlingard^3,4, Mickael Casse³ and Philippe Galy¹

Noise modeling using look-up tables and DC measurements for cryogenic applications.

VLSI-SoC 2023 - 31st IFIP/IEEE International Conference on Very Large Scale Integration,

Oct 2023, Sharjah, United Arab Emirates.

DOI: 10.1109/VLSI-SoC57769.2023.10321896
hal-04305746

1STMicroelectronics, Crolles, France

2Univ. Grenoble Alpes, CNRS, Grenoble-INP, TIMA

3Univ. Grenoble Alpes, CEA, LETI

4Univ. Grenoble Alpes, CNRS, Grenoble-INP, IMEP-LAHC

Abstract : There is today a lack of mature transistor-level compact models for the simulation of integrated circuits at cryogenic temperatures. This is particularly the case for the simulation of the noise behavior which is critical for most applications. In this paper, we aim at an efficient prediction of the white noise behavior of basic amplifying stages working at RF frequencies and cryogenic temperatures. For this, we propose the use of DC measurements that are incorporated in a LookUp Table (LUT) and fed to a mathematical noise model. We illustrate the approach for the case of a transistor in common source configuration. The results of circuit simulation of the noise parameters in the standard temperature range are very close to the estimation of the same parameters using the LUT with just DC measurements. The approach can be readily extended to the analysis of circuits with multiple components. Next, the LUT approach is used for estimating the noise parameters at cryogenic conditions, considering DC measurements that have been carried out at these temperatures. The paper illustrates the feasibility of carrying out a cryogenic design using a LUT-based approach while accurate compact models are not yet available.

Fig : Measurement data and EKV or ACM generated parameters are added

to the LUT generated by the interface between EDA tools

Acknowledgments : This work was supported by the French program Conventions Industrielles de Formation par la Recherche (CIFRE) and Labex MINOS of French program ANR-10-LABX-55-01.

[paper] Unified Model of Shot Noise in the Tunneling Current in Sub-10 nm MOSFETs

Jonghwan Lee

Unified Model of Shot Noise in the Tunneling Current in Sub-10 nm MOSFETs

Nanomaterials 2021, 11, 2759

DOI: 10.3390/nano11102759

  

Department of System Semiconductor Engineering, Sangmyung University, Cheonan 31066, Korea,
  

Abstract: A single unified analytical model is presented to predict the shot noise for both the source to drain (SD) and the gate tunneling current in sub-10 nm MOSFETs with ultrathin oxide. Based on the Landauer formula, the model is constructed from the sequential tunneling flows associated with number fluctuations. This approach provides the analytical formulation of the shot noise as a function of the applied voltages. The model performs well in predicting the Fano factor for shot noise in the SD and gate tunneling currents.

Fig: Comparison between ST model and CT model of Fano factor as a function of Vgs

for (a) SD current noise and (b) gate tunneling current noise.

Funding: This work was supported by the National Research Foundation of Korea (NRF) grant funded by the Korea government (MSIT) (No. 2019R1F1A1050640).