Discover DIH-Network and their services

DIH-World will support the DIHs with training and mentoring and will provide them access to a wide range of good practices. In addition, the Academy will provide tailored support to the participating DIHs and the DIHs selected for the experiments.

Core partners

DIHs

SMEs involved in the pilot experiments

[mos-ak] [Final Program] 14th International MOS-AK Workshop Silicon Valley, Dec. 17, 2021

Final MOS-AK Program 

Together with local host, as well as all the Extended MOS-AK TPC Committee, would like to invite you to the 14th International MOS-AK Workshop Compact/SPICE Modeling Workshop which will be organized as the virtual/online event on Dec.17, 2021, in timeframe of IEDM and Q4 CMC Meetings.

Upcoming online 14th International MOS-AK Workshop aims to strengthen a network and discussion forum among experts in the field, enhance open platform for information exchange related to compact/SPICE modeling and Verilog-A standardization, bring academic and industrial experts in the compact modeling field together, as well as obtain feedback from technology developers, circuit designers, and CAD/EDA tool developers and vendors. 

Final MOS-AK Workshop Program is available online:

https://www.mos-ak.org/silicon_valley_2021/

Online Event Registration Form

https://forms.gle/TQRNjPBWPXGARmSBA

Registered participants will receive online meeting invitation 24h before the event. 

(any related enquiries can be sent to register@mos-ak.org)

Important Dates: 

• Call for Papers: Oct. 2021
• 2nd Announcement: Nov. 2021
• Final Workshop Program: Dec.2 2021
• MOS-AK Workshop: Dec.17, 2021
  in timeframe of IEDM and Q4 CMC Meetings
  (Silicon Valley Time Zone / GMT-8)
  10:00am - 12:30pm MOS-AK Morning Session
  1:00pm - 3:30pm MOS-AK Afternoon Session

Postworkshop Publications: Selected, the best MOS-AK technical presentation will be recommended for further publication in a special Solid State Electronics (SSE) issue on compact modeling.

-- W.Grabinski for Extended MOS-AK Committee

WG071221

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[Open Hardware] [CfP] Computer Aided Modeling and Design Development Room

We are pleased to announce the CfP for the Open Source Computer Aided

Modeling and Design devroom at FOSDEM 2022, on Saturday, 5 February 2022.

FOSDEM website: https://fosdem.org/2022/

FOSDEM Code of Conduct:  https://fosdem.org/2022/practical/conduct/

We hope you'll join us for a full day of talks, demos and interesting
discussions on designing, modeling and testing physical objects using
Open Source tools.  This year's event will be fully virtual (:sad trombone:)
and will feature multiple channels for talks, Q&A as well as
hallway discussions (:happy dance:).

We welcome any talk proposals about the creation of physical objects.

Topics of interest include, but are not limited to:

- Open Hardware projects

- Circuit Design
    * Printed circuit board design tools
    * Circuit simulation
- 3d modeling and analysis
    * Solid modeling tools
    * Meshing, modeling and transforming physical representations
    * Finite element analysis
- 3d printing
    * 3d slicing tools
    * Motor control
- Machine design and integration
    * ECAD/MCAD integration
    * Thermal analysis
    * Wire modeling
- Physical Model Data storage
    * Data representation and optimization
    * Version control in hardware data storage
    * Collaborative and team-based hardware design techniques

Slots will be allocated for short (20 minutes), long (40 minutes)
talks and in-depth (60 minutes).  This includes question time, for which

you should budget at least 20% of your time.

Speakers need to specify their preferred format. Both include time for
questions and answers.

Depending on the number of submissions, submitters may be asked to
utilize an alternate time format.

## The submission process

Please submit your proposals at
https://penta.fosdem.org/submission/FOSDEM22

If you already have a Pentabarf account (for example as a result of
having submitted a proposal in the past), make sure you use it to log in
and submit your proposal. Do not create a new account if you already
have one.

Please include the following information with your submission:

- Abstract
- Preferred Session length
- Speaker bio
- Link to any hardware / code /slides for the talk

When you submit your proposal (creating an "Event" in Pentabarf), make
sure you choose the "Open Source Computer Aided Modeling and Design" in
the track drop-down menu. Otherwise your proposal may go unnoticed.
Fill in at least a title and abstract for the proposed talk and a
suggested duration. Keep in mind that much of the value in these
meetings comes from the discussions, so please allot at least 20%

of the talk time for questions and answers.


## Important dates

- Call for papers available: 29 November 2021
- Call for participation closes: 28 December 2021
- Devroom schedule available: 1 January 2022

- Talk recording uploads due: 20 January 2022

- Devroom day: Saturday 5 February 2022 (09:00 to 17:00)


## Recordings

Because this year's conference will be fully virtual, all talks must be pre-recorded.  These will be verified for sound and video quality prior to the conference.

Each accepted talk will have a dedicated chaperone to help you through the process of recording, encoding and uploading your talk.

The recordings will be published under the same licence as all FOSDEM
content (CC-BY).

_______________________________________________
open-hardware-devroom mailing list
open-hardware-devroom@lists.fosdem.org
https://lists.fosdem.org/listinfo/open-hardware-devroom

[paper] Bridging the gap between design and simulation of low voltage CMOS circuits

C. M. Adornes, D. G. Alves Neto, M. C. Schneider and C. Galup-Montoro

Bridging the gap between design and simulation of low voltage CMOS circuits

2021 IEEE Nordic Circuits and Systems Conference (NorCAS), 2021, pp. 1-5,

DOI: 10.1109/NorCAS53631.2021.9599867

Abstract: This work proposes a simplified MOSFET model based on the Advanced Compact MOSFET (ACM) model, which contains only four parameters to assist the designer in understanding how the main MOSFET parameters affect the design. The 4-parameter model was implemented in Verilog-A to simulate different circuits designed with the ACM model. A CMOS inverter and a ring oscillator were designed and simulated, either using the 4-parameter ACM model or the BSIM model. The simulation results demonstrate that the 4-parameter model is very suitable for ultra-low-voltage (ULV) modeling. In the ultra-low-voltage domain, some of the secondary effects of the MOSFET are not relevant and thus not included in the 4-parameter model. A simplified MOSFET model for the ULV domain is of great importance to applications such as energy harvesting, sensor nodes for the Internet of Things, and always-on circuits.

C. M. Adornes Video Presentation NorCAS 2021

Acknowledgment: The authors would like to thank the Brazilian agencies CAPES, finance code 001, and CNPq for supporting this work.

REF:

[1] A. I. A. Cunha, M. C. Schneider and C. Galup-Montoro, "An MOS Transistor Model for Analog Circuit Design", IEEE J. Solid-State Circuits, vol. 33, no. 10, pp. 1510-1519, October 1998

[2] C. Galup-Montoro and M. C. Schneider, "The compact all-region MOSFET model: theory and applications", IEEE 16th International New Circuits and Systems Conference (NEWCAS), pp. 166-169, June 2018

[3] M. C. Schneider and C. Galup-Montoro, CMOS Analog Design Using All-Region MOSFET Modeling, Cambridge University Press, 2010

[4] C. Galup-Montoro and M. C. Schneider, MOSFET modeling for circuit analysis and design, World Scientific, 2007

[5] Verilog-A Reference Manual, Agilent Technologies, 2004

[6] 0. F. Siebel, "Um modelo eficiente do transistor MOS para o projeto de circuitos VLSI," Universidade Federal de Santa Catarina, Florianopolis, 2007

[7] F. N. Fritsch, R. E. Shafer and W. P. Crowley, "Algorithm 443: Solution of the transcendental equation wew=x," Commun. ACM, vol. 16, no. 2, pp. 123-124, 1973

[8] O. F. Siebel, M. C. Schneider and C. Galup-Montoro, "MOSFET threshold voltage definition, extraction and some applications," Microelectronics Journal, vol. 43, no. 5, pp. 329-336, May 2012

[9] G. Hiblot. DIBL-Compensated Extraction of the Channel Length Modulation Coefficient in MOSFETS. IEEE Transactions on Electron Devices, vol. 65, no. 9, pp. 4015-4018, 2018

[10] BSIM4v4.5.0 Technical Manual, Department of Electrical Engineering and Computer Science, UC Berkeley, Berkeley, CA, USA. 2004

[11] Y. Tsividis and C. McAndrew, Operation and Modeling of the MOS Transistor, Oxford Univ. Press, 2011

[12] J. V. T. Ferreira, C. Galup-Montoro, "Ultra-low-voltage CMOS ring oscillators. Electronics Letters," IET, v. 55, n. 9, p. 523-525,2019

[13] E. M. Camacho-Galeano, C. Galup-Montoro and M. C. Schneider, "A 2-nW 1.1.-V self biased current reference in CMOS technology," IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 52, no. 2, pp. 61-65, 2005

[14] E. Bolzan, E. B. Storck, M. C. Schneider and C. Galup-Montoro, "Design and testing of a CMOS SelfBiased Current Source," 2019 26th IEEE International Conference on Electronics, Circuits and Systems (ICECS), pp. 382-385, 2019

ESSCIRC/ESSDERC 2021 The Best Paper Awards

The #ESSCIRC #ESSDERC TPC is proud to announce The Best Paper Awards from ESSCIRC/ESSDERC 2021 in Grenoble, selected by our Technical Program Committee members:

• BEST JOINT PAPER 2021: “Low Power Indirect Time-of-Flight Pixel Achieving 88.5% Demodulation Contrast at 200MHz for 0.54MPix Depth Camera” by Cedric Tubert et al., STM (F)
• BEST STUDENT JOINT PAPER 2021: “Cryogenic Characterization and Modeling of 14 nm Bulk FinFET Technology”, by @Asma Chabane, IBM Research GmbH
• BEST ESSDERC PAPER 2021: “Complementary Two-Dimensional (2-D) MoS_2 FET Technology”, by @Cristine Jin Estrada et al., The Hong Kong UST
• BEST ESSDERC STUDENT PAPER 2021:“VERILOR: a Verilog-a Model of Lorentzian Spectra for Simulating Trap-Related Noise in CMOS Circuits”, by @Angeliki Tataridou, IMEP-LaHC, Université Grenoble Alpes, University Savoie Mont Blanc, CNRS, Grenoble INP
• BEST ESSCIRC PAPER 2021: “A Resolution-Adaptive 8mm2 9.98Gb/S 39.7pJ/B 32-Antenna All-Digital Spatial Equalizer for mmWave Massive MU-MIMO in 65nm CMOS”, by @Oscar Castaneda et al., ETH Zürich and Cornell Univ.
• BEST ESSCIRC STUDENT PAPER 2021:”A −109.1 dB/−98 dB THD/THD+N Chopper Class-D Amplifier with >83.7 dB PSRR Over the Entire Audio Band”, by @Huajun Zhang et al., TU Delft

Warm congratulations to all the authors, and see you in Milano, September 19-22, 2022 at #ESSCIRC-#ESSDERC Conference for the Award Ceremony!

Sylvain CLERC Francois Andrieu Louis Hutin 

on the behalf off#ESSCIRC #ESSDERC TPC

MPW-4 is open! Deadline is December 31, 2021

[https://t.co/H9QtSVW2z9] MPW-4 is open! Deadline is December 31, 2021. #Free fabrication for #opensource #chip projects. #semi #manufacturing #pdk #IC #SPICE https://t.co/zVCswKFbcL

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Samsung, 2nm will go into mass production in the 2nd Half of 2025

According to Samsung, 2nm will go into mass production in the 2nd Half of 2025 using a 3rd generation Gate-All-Around Field Effect Transistor Architecture (#GAA #FET) [https://t.co/gKjXIv5IPM] #GAAFET #Samsung #Foundry #semi #chips https://t.co/a8sUsp5KLm

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[paper] ACM Model for CMOS Analog Circuits Hand Design

Ademirde Jesus Costa^ab, Eliyas Mehdipour^b, Edson PintoSantana^b,

and Ana Isabela Araújo Cunha^b

Application of Improved ACM Model to the Design by Hand of CMOS Analog Circuits

Microelectronics Journal

Available online 16 November 2021, 105309

DOI: 10.1016/j.mejo.2021.105309

   
a Instituto Federal da Bahia, Santo Amaro, Brazil
b DEEC, Escola Politécnica, Universidade Federal da Bahia, Salvador, Brazil

Abstract: This work aims to provide solutions and perspectives for CMOS analog designers by reducing the time spent in iteratively dimensioning the devices and simulating the circuits. For this purpose, by-hand design methodologies for a few analog cells are proposed employing a MOSFET compact model which has been earlier improved by adding sub-models for some second order effects. A semiempirical sub-model and characterization method is presented for the Early voltage, thus enhancing the set of model equations for hand calculations. The accomplishment of several by-hand design examples and the comparison between simulation results and specifications succeeded in demonstrating the usefulness and advantages of using the improved MOSFET compact model in the proposed methodologies.

Fig: gm/Id Plot

Nanorennes (CNRS)

 

Nanorennes was created in 2007 as a regional micro-technological platform, labelled by french national center of research and science (CNRS). This platform gathers on the same institute the know-how and human beings dedicated to the fabrication of nano-micrometer sized devices, related to two research laboratories located in Rennes : IETR-GM (microelectronic group) and FOTON-OHM (photonic group).

[paper] TFT XNOR/XOR Circuit

E. Bestelink, O. de Sagazan*, I. S. Pesch and R. A. Sporea

Compact Unipolar XNOR/XOR Circuit Using Multimodal Thin-Film Transistors

in IEEE TED, vol. 68, no. 10, pp. 4951-4955, Oct. 2021,

DOI: 10.1109/TED.2021.3103491.

  

Advanced Technology Institute, University of Surrey (UK)

* IETR-DMM-UMR6164, University of Rennes (F)

Abstract: A novel compact realization of the XNOR/ XOR function is demonstrated with multimodal transistors (MMTs). The multimodal thin-film transistors (MMT’s) structure allows efficient use of layout area in an implementation optimized for unipolar thin-film transistor (TFT) technologies, which may serve as a multipurpose element for conventional and emerging large-area electronics. Microcrystalline silicon device fabrication is complemented by physical simulations.

Fig: Micrograph of fabricated microcrystalline MMT devices and circuits. Inset: individual MMT devices with single device (MMT) and two source control gates (SUMFGMMT). Scale bars: 500μm.

Acknowledgement: Devices were fabricated on the NanoRennes platform.

CCBY - IEEE is not the copyright holder of this material. 

My Story of Raja Manickam, CEO of OSAT, Tata Electronics

For the November issue, Electronicsforu.com Network shares My Story of Raja Manickam who is CEO of OSAT, Tata Electronics.

CLICK HERE to read it.

Rahul Chopra Editor,

Electronicsforu.com Network | EFY Group | New Delhi | India |

[mos-ak] 2nd Announcement and C4P] 14th International MOS-AK Workshop Silicon Valley, Dec. 17, 2021

Arbeitskreis Modellierung von Systemen und Parameterextraktion 

Modeling of Systems and Parameter Extraction Working Group

14th International MOS-AK Workshop

Silicon Valley, Dec. 17, 2021

2nd Announcement and C4P

Together with local host, as well as all the Extended MOS-AK TPC Committee, would like to invite you to the 14th International MOS-AK Workshop Compact/SPICE Modeling Workshop which will be organized as the virtual/online event on Dec.17, 2021, in timeframe of IEDM and Q4 CMC Meetings.

Planned virtual 14th International MOS-AK Workshop aims to strengthen a network and discussion forum among experts in the field, enhance open platform for information exchange related to compact/SPICE modeling and Verilog-A standardization, bring academic and industrial experts in the compact modeling field together, as well as obtain feedback from technology developers, circuit designers, and CAD/EDA tool developers and vendors. 

Topics to be covered include the following among other related to the compact/SPICE modeling and its Verilog-A standardization:

• Compact Modeling (CM) of the electron devices
• Advances in semiconductor technologies and processing
• Verilog-A language for CM standardization
• New CM techniques and extraction software
• Open Source (FOSS) TCAD/EDA modeling and simulation
• CM of passive, active, sensors and actuators
• Emerging Devices, Organic TFT, CMOS and SOI-based memory
• Microwave, RF device modeling, high voltage device modeling
• Nanoscale CMOS, BiCMOS, SiGe, GaN, InP devices and circuits
• Technology R&D, DFY, DFT and reliability/aging IC designs
• Foundry/Fabless Interface Strategies

Online Abstract Submission to be open (any related enquiries can be sent to abstracs@mos-ak.org)

Online Event (any related enquiries can be sent to register@mos-ak.org)

Important Dates: 

• Call for Papers: Oct. 2021
• 2nd Announcement: Nov. 2021
• Final Workshop Program: Dec.2 2021
• MOS-AK Workshop: Dec.17, 2021
  in timeframe of IEDM and Q4 CMC Meetings

W.Grabinski for Extended MOS-AK Committee

WG171121

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[https://t.co/phyxhOdhdm] Duisburg RISC-V 4th International Meetup https://t.co/YdSvOTXMUG #serv #riscv #fossi #fusesoc #semi #chips https://t.co/nnZywb4LEk

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[https://t.co/sIRWwTkifR] The #Chip That Could #Transform #Computing #semi #semiconductors #manufacturing https://t.co/SxOqFf712o

[https://t.co/sIRWwTkifR] The #Chip That Could #Transform #Computing #semi #semiconductors #manufacturing https://t.co/SxOqFf712o

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The Semiconductor Manufacturing Road Map For India (by Chetan Arvind Patil ) #semiconductorindustry #semi #technology #manufacturing #ic #icdesign #foundry #foundries #idm #chips https://t.co/dxkDdFbqd4

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[paper] Extended gate FET pH Sensor

Shaiful Bakhtiar Hashim, Zurita Zulkifli, Sukreen Hana Herman

Design and Simulation of Electrochemical Equivalent Circuit for Extended gate FET pH Sensor Based on Experimental Value Using LTSPICE XVII

researchsquare.com: November 11th, 2021

DOI:10.21203/rs.3.rs-1031896/v1

  
College of Engineering, UiTM, Selangor (MY)

Abstract: A SPICE model for extended-gate field-effect transistor (EGFET) based pH sensor was developed using standard discrete components. Capacitors and resistors were used to represent the sensing and reference electrodes in the EGFET sensor system and the values of the discrete component were varied to see the output of the transistor. These variations were done to emulate the EGFET sensor output in different pH values. It was found that the experimental transfer and output characteristics of the EGFET were very similar to those from the SPICE simulation. Other than that, the changes of value components in the equivalent circuit did not affect the transfer and output characteristics graph, but the capacitor value produced significant output variation in the simulation. This can be related to the modification on the equivalent circuit was done with additional voltage, VSB (source to bulk) to produce the different VT values at different pH.

Fig: EGFET measurement setup

Acknowledgement: The work is partially supported by KEPU Grant ( 600- RMC/KEPU 5/3 (007/2021)) from Universiti Teknologi MARA

[C4P] FLEPS 2022

Call for Papers

The IEEE International Conference on Flexible, Printable Sensors and Systems (FLEPS 2022) will be held in Vienna, Austria.

IEEE FLEPS 2022 is intended to provide a forum for research scientists, engineers, and practitioners throughout the world to present their latest research findings, ideas, and applications in the area of Flexible and Printable Sensors and Systems.

Topics of Interest

• Organic/Inorganic Electronic Sensors
• Emerging Materials for Flexible and Printable Systems
• Manufacturing Techniques
• High-throughput Printable Electronics
• Hybrid Flexible Sensors and Electronics
• Stretchable/Shrinkable Sensors and Electronics
• Soft/Smart Wearable and Implantable Sensing Systems
• Disposable/Reusable Sensors and Electronics
• Printed Large-Area Sensors and Systems
• Flexible or Printed Active and Passive Components (e.g. actuators, printed energy devices, smart labels, RFID etc.)
• Emerging applications of Flexible Electronics inc. IoT, smart cities etc.
• Simulation and Modelling
• Flexible/Printable Electronics in context with Circular Economy and green electronics

Publication of Papers: Presented papers will be included in the Proceedings of IEEE FLEPS 2022 and in IEEE Xplore pending author requirements being met. Authors may submit an extended IEEE FLEPS 2022 papers to the Special IEEE FLEX Journal Issue.

Exhibition & Patron Opportunities: The Conference exhibit area will provide your company or organization with the opportunity to inform and display your latest products, services, equipment, books, journals, and publications to attendees from around the world.

For further information, contact Coral Miller at Conference Catalysts, LLC.

[paper] Nanoscale InGaAs FinFETs

Jesús A. del Alamo1, Xiaowei Cai1,2, Xin Zhao1, Alon Vardi1, and Jesús Grajal3

Nanoscale InGaAs FinFETs: Band-to-Band Tunneling and Ballistic Transport

51st European Solid-State Device Research Conference, Grenoble 2021

   
1: Microsystems Technology Laboratories, MIT, Cambridge (USA)
2: Analog Devices, Inc., (USA)
3: IPT Center, Universidad Politécnica de Madrid (SP)

Abstract: InGaAs is an attractive material for high-speed, high-frequency electronics and ultra-low-noise applications. A great effort has taken place recently towards the development of high-performance InGaAs MOSFETs with different geometries: planar MOSFETs, FinFETs and Nanowire MOSFETs. This exploration has uncovered a number of interesting device physics of relevance to the development of electronics based on other material systems. InGaAs is a narrow bandgap material. As such, it is prone to excess band-to-band tunneling at moderate voltages. Due to the floating nature of the InGaAs MOSFET body, holes generated by BTBT cannot escape from the body. Through a parasitic lateral bipolar transistor that is hiding inside the MOSFET, this results in excess off-state current, which compromises transistor logic operation. InGaAs also features a very small effective mass. This yields prominent ballistic effects in nanoscale devices. Towards studying this, we have developed a new technique to extract mobility and injection velocity in InGaAs MOSFETs in the presence of severe gate oxide trapping, as is the case in the high-k/InGaAs MOS system. In InGaAs FinFETs, we find a degradation in scattering limited mobility but an enhancement in ballistic mobility as the fin-width narrows. Also, the injection velocity shows no discernable fin width dependence. An important lesson from these studies is that long channel mobility measurements constitute a poor predictor of short-channel performance of InGaAs FinFETs.

Fig: Cross section of self-aligned InGaAs FinFETs on InP (left) along and (right) across the fin. The intrinsic channel is In_0.53Ga_0.47As and it is nominally undoped. These are double-gate devices.

Acknowledgment: Research sponsored by DTRA (#HDTRA 1-14-1-0057), NSF (E3S STC Award 0959514), MISTI, KIST and Lam Research. Devices fabricated in MIT’s Microsystems Technology Laboratories and EBL.

The panel: #UK Should Emulate #Israel for #Semiconductor #Startups to Succeed

The panel: Where are we now, where do we want to go? #UK Should Emulate #Israel for #Semiconductor #Startups to Succeed - EE Times Europe https://t.co/LpfK6H2mnU #semi #chips https://t.co/SPuqTG2p4W

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[book] Future Ultra Low Power Electronics

Semiconductor Devices and Technologies for Future Ultra Low Power Electronics (1st ed.)

Nirmal, D., Ajayan, J., & Fay, P.J. (Eds.)

CRC Press. (2021).

DOI: 10.1201/9781003200987

Abstract: This book covers the fundamentals and significance of 2-D materials and related semiconductor transistor technologies for the next-generation ultra low power applications. It provides comprehensive coverage on advanced low power transistors such as NCFETs, FinFETs, TFETs, and flexible transistors for future ultra low power applications owing to their better subthreshold swing and scalability. In addition, the text examines the use of field-effect transistors for biosensing applications and covers design considerations and compact modeling of advanced low power transistors such as NCFETs, FinFETs, and TFETs. TCAD simulation examples are also provided. 

Contents:

Preface vii

Editors ix

Contributors xi

Chapter 1: An Introduction to Nanoscale CMOS Technology Transistors: A Future Perspective; pp: 1

Kumar Prasannajit Pradhan

Chapter 2: High-Performance Tunnel Field-Effect Transistors (TFETs) for Future Low Power Applications; pp: 29

Ribu Mathew, Ankur Beohar, and Abhishek Kumar Upadhyay

Chapter 3: Ultra Low Power III-V Tunnel Field-Effect Transistors; pp: 59

J. Ajayan and D. Nirmal

Chapter 4: Performance Analysis of Carbon Nanotube and Graphene Tunnel Field-Effect Transistors; pp: 87

K. Ramkumar, Singh Rohitkumar Shailendra, and V. N. Ramakrishnan

Chapter 5: Characterization of Silicon FinFETs under Nanoscale Dimensions; pp: 115

Rock-Hyun Baek and Jun-Sik Yoon

Chapter 6: Germanium or SiGe FinFETs for Enhanced Performance in Low Power Applications; pp: 129

Nilesh Kumar Jaiswal and V. N. Ramakrishnan

Chapter 7: Switching Performance Analysis of III-V FinFETs .; pp: 155

Arighna Basak, Arpan Deyasi, Kalyan Biswas, and Angsuman Sarkar

Chapter 8: Negative Capacitance Field-Effect Transistors to Address the Fundamental Limitations in Technology Scaling; pp: 187

Harsupreet Kaur

Chapter 9: Recent Trends in Compact Modeling of Negative Capacitance Field-Effect Transistors; pp: 203

Shubham Tayal, Shiromani Balmukund Rahi, Jay Prakash Srivastava, and Sandip Bhattacharya

Chapter 10 Fundamentals of 2-D Materials; pp: 227

Ganesan Anushya, Rasu Ramachandran, Raj Sarika, and Michael Benjamin

Chapter 11 Two-Dimensional Transition Metal Dichalcogenide (TMD) Materials in Field-Effect Transistor (FET) Devices for Low Power Applications; pp 253

R. Sridevi and J. Charles Pravin

Index pp: 289

[paper] Verilog-A Compact MTJ Model

Etienne Becle, Philippe Talatchian, Guillaume Prenat, Lorena Anghel, Ioan-Lucian Prejbeanu 

Fast Behavioral VerilogA Compact Model for Stochastic MTJ  

51st European Solid-State Device Research Conference; Grenoble 2021

  

CEA-Spintec (F)

Abstract: Spin-Transfer Torque Magnetic Tunnel Junctions (STT-MTJ) are devices featuring stochastic properties. They are promising candidates for non-volatile memory or true random number generators. To design reliable hybrid CMOS circuits including STT-MTJs, one needs to use a compact model accounting for its stochasticity in the circuit simulations. This paper proposes a compact model that accurately mimics the MTJ stochastic switching behavior and meets the needs of fast execution time. The relevance of such a model together with its fast execution velocity are illustrated with a bitstream generator. 

Fig: Schematic representation of the implemented algorithm

Acknowledgement: This work is supported by the French National Research Agency in the framework of the "Investissements d’avenir” program (ANR-15-IDEX-02). 

Advances in RF and THz emerging electronic devices webinar at IPN-UAB

The webinar joitly co-organize together with Instituto Politécnico Nacional, Mexico 

is intended to present and discuss recent advances in RF and THz emerging electronic devices.

Feel free to share the information with your colleagues and/or students. The registration is free, and you can do it here (it is in Spanish but the only required fields are Name, Surname, Email, and Email confirmation). Alternatively, you can follow the live stream in this youtube channel.

The time appearing in the flyers are referred to Mexico City's time. The schedule is starting each day Nov.16-18, 2021 at 16 hrs CET.

If you have further questions you can contact 

• Aníbal Uriel Pacheco Sanchez or 
• Eloy Ramirez Garcia, IPN co-organizer

   

Career opportunities at VTT

Career opportunities at 

VTT Microelectronics and Quantum Technologies 

Apply by 14.11.2021

VTT is one of the leading research organizations in Europe and we are operating the largest R&D cleanroom in the Nordic countries, located in Micronova premises, Espoo. We develop innovative micro, nano and quantum systems and algorithms and software driven by different sensing, communication and computing applications. A timely example being the building of Finland's first quantum computer. We work closely with global industrial and academic players of different fields of technology. What unites us at VTT are the curiosity, passion of learning and devotion to finding solutions to global challenges and answers to our customers' needs. You can familiarize with us further by exploring VTT's research infra through VTT World.

Due to our continual growth, we are currently seeking for more than 15 new talents in microelectronics and quantum technologies to join our team. If you are interested in joining VTT, read more about job opportunities using links below:  

• Summary of all job openings in Microelectronics and Quantum Technologies teams
• Research Scientist, Superconducting Quantum Circuits
• Research Scientist, Quantum Hardware Development
• Senior / Research Scientist, Digital Electronics and Embedded Software 
• Research Scientist, Quantum Algorithms and Software
• Research Scientist, Neuromorphic Computing Algorithms and Software
• Research Scientist, Nanoelectronic Devices
• Research Scientist, Photonic and Thermal Devices
• Two Senior / Research Scientists, Analog IC Design for Neuromorphic Computing
• Research Scientist, Silicon Photonics Process Integration
• Research Scientist, Optical Computing and Quantum Photonics Hardware
• Research Technicians, Cleanroom
• Mechanical Designer
• Master's Thesis Worker, Low Temperature Physics
• Master's Thesis Worker, Photonic and Thermal Devices
• Master's Thesis Worker, Nanoelectronic Devices
• Master's Thesis Worker, Graphene Quality Control

 

Best regards

 

Matteo Cherchi, PhD

Senior Scientist

Silicon photonics

Tel. +358 40 6849040

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vttresearch.com

 

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[paper] InP HEMTs for future THz applications

J.Ajayan^a, D.Nirmal^b, Ribu Mathew^c, Dheena Kurian^d, P.Mohankumar^e, L.Arivazhagan^b, D.Ajitha^f

A critical review of design and fabrication challenges in InP HEMTs 

for future terahertz frequency applications

Materials Science in Semiconductor Processing

Volume 128, 15 June 2021, 105753

  
a SR University, Warangal, Telangana, India
b Karunya Institute of Technology and Sciences, Coimbatore, Tamilnadu, India
c VIT Bhopal University, Bhopal, Madhya Pradesh, India
d Kerala Technological University, Trivandrum, Kerala, India
e Sona College of Technology, Salem, Tamilnadu, India
f Sreenidhi Institute of Science and Technology, Hyderabad, Telangana, India

Abstract: This article critically reviews the materials, processing and reliability of InP high electron mobility transistors (InP HEMTs) for future terahertz wave applications. The factors such as drain current (ID) over 1200 mA/mm, transconductance (gm) over 3000 mS/mm, cut off frequency (fT) over 700 GHz and maximum oscillation frequency (fmax) over 1300 GHz makes InP HEMTs suitable for Terahertz wave applications. Furthermore, low DC power consumption and outstanding low noise performance makes InP HEMT most appropriate transistor technology for the development of space based receivers. This review article critically assesses the challenges in miniaturization of InP HEMTs, doping strategies in InP HEMTs, buried platinum technology, impact of annealing process and temperature, influence of electron and proton irradiation, thermal and bias stress on the reliability of InP HEMTs, cavity and gating effects and influence of trapping effects. InP HEMTs are very much preferable in applications like radio astronomy, terahertz optical and wireless communication systems, atmospheric imaging and sensing, automotive radar, ground based receivers in deep space networks, terahertz imaging and sensing, biomedical applications, security screening, video conferencing & real time multimedia file transfer, high speed and ultra low power digital integrated circuits.

Fig: 3D representation of InP high electron mobility transistor (InP HEMT)