[paper] Abstraction NBTI model

Stephan Adolf and Wolfgang Nebel

Abstraction NBTI model

it - Information Technology, Sep. 2021

DOI: 10.1515/itit-2021-0005

Abstract: Negative Bias Temperature Instability (NBTI) is one of the major transistor aging effects, possibly leading to timing failures during run-time of a system. Thus, one is interested in predicting this effect during design time. In this work, an Abstraction NBTI model is introduced reducing the state space of trap-based NBTI models using two abstraction parameters, applying a state transformation to incorporate variable stress conditions. This transformation is faster than traditional approaches. Currently, the conversion into estimated threshold voltage damages is a very time-consuming process.

Fig: Trap in the gate oxide of a PMOS transistor

Acknowledgement: The author thanks Kim Grüttner for proofreading the manuscript of the paper. This research is funded by the German Research Foundation through the Research Training Group “SCARE: System Correctness under Adverse Conditions” (DFG-GRK 1765/2), https://www.uni-oldenburg.de/en/scare/. The simulations were partly performed on the HPC Cluster CARL at the University of Oldenburg (Germany), funded by the DFG through its Major Research Instrumentation Program (INST 184/157-1 FUGG) and the Ministry of

Science and Culture (MWK) of the Lower Saxony State.

Generalized EKV Compact MOSFET Model

On the Explicit Saturation Drain Current in the Generalized EKV Compact MOSFET Model

Francisco J. García-Sánchez, Life Senior Member, IEEE,

and Adelmo Ortiz-Conde, Senior Member, IEEE

IEEE TED Aug 9. 2021

DOI: 10.1109/TED.2021.3101186

*Solid State Electronics Laboratory, Universidad Simón Bolívar, Caracas 1080, Venezuela

Abstract: We present and discuss explicit closed-form expressions for the saturation drain current of short channel metal-oxide-semiconductorfield-effect transistors (MOSFETs) with gate oxide and interface-trapped charges, and including carrier velocity saturation, according to the generalized Enz-Krummenacher-Vittoz (EKV) MOSFET compact model. The normalized saturation drain current is derived as an explicit function of the normalized terminal voltages by solving the transcendental voltage versus charge equation using the Lambert W function. Because this special function is analytically differentiable, other important quantities, such as the transconductance and the transconductance-to-currentratio, can be readily expressed as explicit functions of the terminal voltages.

Fig: Comparison of simulated transfer characteristics with (red lines and symbols) and another without (black lines and symbols) radiation-induced oxide and interface-trapped charges. Calculation of V_GB versus ID_sat (lines) comes from denormalization and the explicit ID_sat versus V_GB (symbols) comes from denormalization of the proposed explicit expressions

[paper] Model for Ultra-Scaled MoS2 MOSFET

Weiran Cai, Wenrui Lan, Zichao Ma*, Lining Zhang, Mansun Chan*

A Full-region Model for Ultra-Scaled MoS2 MOSFET Covering Direct Source-Drain Tunneling 

9th International Symposium on Next Generation Electronics (ISNE), 2021, pp. 1-3,

DOI: 10.1109/ISNE48910.2021.9493621

College of Electronic and Information Technology, Shenzhen University, Shenzhen, China

* Hong Kong University of Science and Technology, Hong Kong, China

Abstract: A full-region model for ultra-scaled monolayer MoS2 MOSFETs is reported in this work. The electrostatic potential in the scaled transistor structure is analyzed based on a first-principle verified potential model. A continuous full region current model is then developed to capture the short channel effects. Based on the potential model, the barrier height and width for direct source-drain tunneling are obtained. The direct tunneling module reproduces the essential physics observed from numerical device simulations. After integration with the thermionic emission model, the full-region current model is implemented into a SPICE simulator and the model convergence is verified by simulating typical circuits.

A drift-diffusion current model of the full region is straightforwardly derived with Taylor expansions of a Si model or from the Pao-Sah integral. It resembles the EKV current model and allows similar expressions of small signal models:

Fig: The impact of SCEs on devices of different channel length is showed in (a) Ids–Vg and (b) Ids–Vd characteristics predicted by the model covering SCEs. When channel length becomes smaller, SCEs becomes more serious. 

Acknowledgement: This work is supported in part by the Natural Science Foundation of China under Grant 61704144, the Shenzhen Science and Technology Project under JCYJ20180305125340386, the General Research Fund (GRF) from Research Grant Council (RGC) of Hong Kong under Grant 16206219

[PhD] Cryogenic MOSFET Modeling

Cryogenic MOSFET Modeling for Large-Scale Quantum Computing

Arnout Lodewijk M BECKERS

Thèse n° 8365 2021

DOI: 10.5075/epfl-thesis-8365

Présentée le 28 mai 2021

Faculté des sciences et techniques de l’ingénieur Laboratoire de circuits intégrés Programme doctoral en génie électrique

pour l’obtention du grade de Docteur ès Sciences par

Arnout Lodewijk M BECKERS

Acceptée sur proposition du jury:

Prof. E. Charbon, président du jury
Prof. C. Enz, directeur de thèse
Prof. B. Parvais, rapporteur
Prof. G. Ghibaudo, rapporteur
Dr J.-M. Sallese, rapporteur 

Abstract: Promising results of state-of-the-art quantum computers fuel a world-wide effort in academic and private research laboratories to scale up the number of qubits and improve their characteristics in large arrays. To meet the scale-up challenge, innovative microelectronic architectures are envisioned hosting qubits and transistors in silicon. Integrated-circuit design for deep-cryogenic temperatures (below 10 K or -263.15°C) is a challenging optimization exercise that currently leads to costly iterations due to the lack of physics-based transistor models for these temperatures. Proposed enhancements to the industry-standard transistor models neglect the low-temperature physics and do not suffice for a large-volume application. This PhD thesis pushes the state-of-the-art of the characterization, physics, and modeling of CMOS (Complementary Metal Oxide Semiconductor) transistors down to deep-cryogenic temperatures. The most advanced commercial bulk CMOS technology (28-nm minimum gate length) is measured down to 4.2 K using dip-stick measurements and probe-station measurements. The temperature behavior of the physical parameters and the analog figures-of-merit is reported. A similar characterization study is presented for a 28-nm FDSOI CMOS technology using measurements provided by CEA-Léti through the EU H2020 MOS-Quito Project. It is shown that the design methodology based on the transconductance efficiency remains valid down to 4.2 K for both advanced CMOS processes. These results are already supporting the community: qubit controllers in 28-nm bulk and FDSOI technologies have been successfully deployed in the cryostats of quantum computers by Google and CEA-Léti, respectively. Industry-standard models have been honed over many years for near room-temperature operation. They show the largest discrepancies in the sub- and near-threshold regimes when used at deep-cryogenic temperatures. Therefore, this thesis presents an in-depth study of these regimes. Generalized Boltzmann relations are derived including band tails, which are valid in subthreshold. Using these relations, a new analytical theory is derived for the subthreshold swing that rolls off from the Boltzmann limit, showing that an ideal step-like switch cannot be obtained in the 0-K limit due to shallow band-edge states. The process quality must be improved to operate devices closer to the Boltzmann limit. Moreover, the transconductance efficiency in weak inversion (subthreshold) follows the new theoretical limit instead of the Boltzmann temperature limit. This mitigates the expected current savings from biasing in weak inversion. The new theory also explains the impossible inverse temperature dependence of the subthreshold-slope factor, which has been extracted in numerous characterizations in the literature. Furthermore, a threshold-voltage model for bulk CMOS is presented including dopant freezeout and interface traps. Process engineers can benefit from this model to customize transistors for use at 4.2 K. Finally, the discrepancy of the transfer characteristics in moderate inversion (near-threshold) is modeled with an improved representation of the localized band-edge states. As such, this PhD thesis lays the groundwork for next-generation deep-cryogenic IC design benefiting from physics-based knowledge. While this thesis is oriented toward quantum computing, the results also apply to other deep-cryogenic applications at the forefront of science and engineering.

Fig: Different explanations have been proposed for the deviation of the subthreshold swing (SS) from the Boltzmann limit at deep-cryogenic temperatures (below a critical temperature Tc). This led to the introduction of band-edge states to explain SS(T)

[paper] MOSFET Threshold Voltage Extraction

Nikolaos Makris and Matthias Bucher (IEEE Member)

On MOSFET Threshold Voltage Extraction 

Over the Full Range of Drain Voltage Based on Gm/ID

arXiv:2106.00747v1 [physics.app-ph] 1 June 2021

Abstract: A MOSFET threshold voltage extraction method covering the entire range of drain-to-source voltage, from linear to saturation modes, is presented. Transconductance-to-current ratio is obtained from MOSFET transfer characteristics measured at low to high drain voltage. Based on the charge-based modeling approach, a near-constant value of threshold voltage is obtained over the whole range of drain voltage for ideal, long-channel MOSFETs. The method reveals a distinct increase of threshold voltage versus drain voltage for halo-implanted MOSFETs in the low drain voltage range. The method benefits from moderate inversion operation, where high-field effects, such as vertical field mobility reduction and series resistances, are minimal. The present method is applicable over the full range of drain voltage, is fully analytical, easy to be implemented, and provides more consistent results when compared to existing methods.

Fig: Extraction of threshold voltage for a long-channel MOSFET from transconductance-to-current ratio (TCR) covering linear to saturation modes. (a) GmUT /ID obtained from ID vs. VG characteristics measured at different values of VDS (long-channel n-MOSFET) together with model (b) Criterion for threshold voltage nGmUT /ID varies among two asymptotic values in linear and saturation modes.

Aknowlegements: This work was partly supported under Project INNOVATION-EL-Crete (MIS 5002772).

Related papers:

[i] T. Rudenko, V. Kilchytska, M. K. M. Arshad, J. Raskin, A. Nazarov and D. Flandre, "On the MOSFET Threshold Voltage Extraction by Transconductance and Transconductance-to-Current Ratio Change Methods: Part I—Effect of Gate-Voltage-Dependent Mobility," in IEEE Transactions on Electron Devices, vol. 58, no. 12, pp. 4172-4179, Dec. 2011.

doi: 10.1109/TED.2011.2168226

[ii] T. Rudenko, V. Kilchytska, M. K. M. Arshad, J. Raskin, A. Nazarov and D. Flandre, "On the MOSFET Threshold Voltage Extraction by Transconductance and Transconductance-to-Current Ratio Change Methods: Part II—Effect of Drain Voltage," in IEEE Transactions on Electron Devices, vol. 58, no. 12, pp. 4180-4188, Dec. 2011.

doi: 10.1109/TED.2011.2168227

[iii] T. Rudenko, V. Kilchytska, M. K. M. Arshad, J. Raskin, A. Nazarov and D. Flandre, "Influence of drain voltage on MOSFET threshold voltage determination by transconductance change and gm/Id methods," ULIS, Cork, Ireland, 2011, pp.1-4.

doi: 10.1109/ULIS.2011.5758012

[papers] Aging and Device Reliability Compact Modeling

IEEE International Reliability Physics Symposium

(IRPS 2021)

[1] N. Chatterjee, J. Ortega, I. Meric, P. Xiao and I. Tsameret, "Machine Learning On Transistor Aging Data: Test Time Reduction and Modeling for Novel Devices," 2021 IEEE International Reliability Physics Symposium (IRPS), 2021, pp. 1-9, doi: 10.1109/IRPS46558.2021.9405188.

Abstract: Accurately modeling the I-V characteristics and current degradation for transistors is central to predicting circuit end-of-life behavior. In this work, we propose a machine learning model to accurately model current degradation at various stress conditions and extend that to make nominal use-bias predictions. The model can be extended to track and predict any parametric change. We show an excellent agreement of the model with experimental results. Furthermore, we use a deep neural network to model the I-V characteristics of aged transistors over a wide drain and gate playback bias range and show an excellent agreement with experimental results. We show that the model is reliably able to interpolate and extrapolate demonstrating that it learns the underlying functional form of the data.

URL: https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=9405188&isnumber=9405088

[2] P. B. Vyas et al., "Reliability-Conscious MOSFET Compact Modeling with Focus on the Defect-Screening Effect of Hot-Carrier Injection," 2021 IEEE International Reliability Physics Symposium (IRPS), 2021, pp. 1-4, doi: 10.1109/IRPS46558.2021.9405197.

Abstract: Accurate prediction of device aging plays a vital role in the circuit design of advanced-node CMOS technologies. In particular, hot-carrier induced aging is so complicated that its modeling is often significantly simplified, with focus limited to digital circuits. We present here a novel reliability-aware compact modeling method that can accurately capture the full post-stress I-V characteristics of the MOSFET, taking into account the impact of drain depletion region on induced defects.

URL: https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=9405197&isnumber=9405088

[3] Z. Wu et al., "Physics-based device aging modelling framework for accurate circuit reliability assessment," 2021 IEEE International Reliability Physics Symposium (IRPS), 2021, pp. 1-6, doi: 10.1109/IRPS46558.2021.9405106.

Abstract: An analytical device aging modelling framework, ranging from microscopic degradation physics up to the aged I-V characteristics, is demonstrated. We first expand our reliability oriented I-V compact model, now including temperature and body-bias effects; second, we propose an analytical solution for channel carrier profiling which-compared to our previous work-circumvents the need of TCAD aid; third, through Poisson's equation, we convert the extracted carrier density profile into channel lateral and oxide electric fields; fourth, we represent the device as an equivalent ballistic MOSFETs chain to enable channel “slicing” and propagate local degradation into the aged I-V characteristics, without requiring computationally-intensive self-consistent calculations. The local degradation in each channel “slice” is calculated with physics-based reliability models (2-state NMP, SVE/MVE). The demonstrated aging modelling framework is verified against TCAD and validated across a broad range of VG/VD/T stress conditions in a scaled finFET technology.

URL: https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=9405106&isnumber=9405088

[paper] An Accurate Analytical Modeling of Contact Resistances in MOSFETs

G. Bokitko, D. S. Malich, V. O. Turin*, and G. I. Zebrev

An Accurate Analytical Modeling of Contact Resistances in MOSFETs

Preprint · May 7, 2021 DOI: 10.13140/RG.2.2.29348.40321

National Research Nuclear University MEPHI, Moscow, Russia;
*Orel State University, Russia;

Abstract: As the MOSFET channel lengths decrease, the influence of parasitic source-drain resistance on the current characteristics becomes more and more important. The contact resistance is becoming a growing impediment to transistor power and performance scaling. This is a common challenge for SOI FETs, FinFETs and GAAFETs and any other type of transistor. Most of the modern compact models that are used in circuits simulations are too much technology oriented. We find it important to construct an analytical approach that could be served as a basis for compact modeling. This approach is based on analytical solution Kirchhoff’s equations and on the diffusion-drift field effect transistor model.

Fig: Equivalent MOSFET circuit with series resistance

[papers] Compact Modeling

[1] Zhang, Yuanke, Tengteng Lu, Wenjie Wang, Yujing Zhang, Jun Xu, Chao Luo, and Guoping Guo. "Characterization and Modeling of Native MOSFETs Down to 4.2 K." arXiv:2104.03094 (2021).

Abstract: The extremely low threshold voltage (VTH) of native MOSFETs (VTH≈0 V @ 300 K) is conducive to the design of cryogenic circuits. Previous research on cryogenic MOSFETs mainly focused on the standard threshold voltage (SVT) and low threshold voltage (LVT) MOSFETs. In this paper, we characterize native MOSFETs within the temperature range from 300 K to 4.2 K. The cryogenic VTH increases up to ∼0.25 V (W/L = 10 µm/10 µm) and the improved subthreshold swing (SS) ≈ 14.30 mV/dec @ 4.2 K. The off-state current (IOFF) and the gate-induced drain leakage (GIDL) effect are ameliorated greatly. The step-up effect caused by the substrate charge and the transconductance peak effect caused by the energy quantization in different subbands are also discussed. Based on the EKV model, we modified the mobility calculation equations and proposed a compact model of large size native MOSFETs suitable for the range of 300 K to 4.2 K. The mobility-related parameters are extracted via a machine learning approach and the temperature dependences of the scattering mechanisms are analyzed. This work is beneficial to both the research on cryogenic MOSFETs modeling and the design of cryogenic CMOS circuits for quantum chips.

Fig: I-V curves of native MOSFETs with W/L= 10/10µm measured (symbol) and calculated (solid line) at various temperatures. (a) Acomparison of the calculation results between this model and the  EKV2.6 model at 77K and 4.2K. (b) Measurement and calculation results of  the output characteristic at 4.2 K.

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[2] Qixu Xie  Guoyong Shi; An analytical gm/ID‐based harmonic distortion prediction method for multistage operational amplifiers; Int J Circ Theor Appl. 2021; 1– 27. DOI: 10.1002/cta.3012

Abstract: An analytical stage‐based harmonic distortion (HD) analysis method for multistage operational amplifiers (Op Amps) is developed in this work. This work contributes two fundamental methods that make the analytical HD prediction possible at the circuit level. Firstly, we propose that the traditionally used first order small‐signal transistor quantities gm (transconductance) and go (output conductance) in the gm/ID design methodology for bulk complementary metal‐oxide‐semiconductor (CMOS) technology can be extended to the higher order quantities gm(k) and go(k) (k=1,2,3). With proper normalization, these quantities become neutral to the device dimensions and operation currents, hence can be precharacterized by sweeping simulations and used as lookup tables. Secondly, we further develop analytical nonlinearity expressions for a set of commonly used amplifier stages, represented as the functions of the nonlinearity parameters gm(k) and go(k) of the transistors that form a stage circuit. A combination of these two fundamental methods on hierarchical nonlinearity modeling enables us to apply the existing analytical HD estimation methods for the stage‐form macromodels to predict the circuit‐level HD behavior, overcoming the need of running repeated simulations under device resizing and rebiasing. The proposed harmonic distortion analysis method has been validated by application to real multistage amplifiers, achieving HD prediction results in excellent agreement to fully transistor‐level circuit simulation results but with substantial speedup.

[papers] compact modeling

Rabnawaz Sarmad Uqaili, Faraz Bashir Soomro, Junaid Ahmed Uqaili, Ahsin Murtaza Bughio 

and Khalid Ali Khan

Study on Compact Equivalent Circuit Model for RF CMOS Transistor 

International Journal of Scientific & Technology Research 

Vol.10, Issue 02, February 2021 ISSN 2277-8616

Abstract: In this study, a physical-based radio-frequency (RF) compact equivalent circuit model (CECM) for complementary metal-oxidesemiconductor (CMOS) transistor and its parameter extraction is presented. The whole structure of CECM that includes a small-signal equivalent circuit model of the transistor, a MOSFET small-signal substrate model, an input and output ground-signal-ground (GSG) pad model, a pad coupling model and a metal interconnection model are briefly studied and discussed. Based on this study, a complete test structure model for RF CMOS is designed and the initial values of parameters are extracted by using the analytical method. The multi-bias scattering parameters (S-Parameters) of model correspondence to the experimentation are validated up to 66 GHz and 220 GHz respectively. A good agreement has been achieved between the simulation and experimental under multi-bias conditions.

Fig: Complete CECM for RF CMOS transistor with an entire test structure.

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El Mashade, Mohamed B., and Ahmed Abdel Monem

Transient model for modern microelectronic devices applicable to EKV PMOS model 

Radioelectronics and Communications Systems 

Vol.64, no. 2 (2021): 64-79

Abstract: Massive advances in microelectronic manufacturing technology with an exponential growth of their complexity and speed are needed to ensure a continuous development of novel techniques, structures, devices, circuits and systems. This paper is intended for the introduction of a new PMOS transient model for modern microelectronic devices that provides a fast transient response. Such suggested model expresses the transient terminal currents as polynomial functions of the normalized channel charge densities at the channel bounds with the assistance of a modified version of the cubic spline collocation methodology in symmetrical telescopic fashion. Additionally, the optimum number of segments, which is suitable for the new version of the cubic spline collocation algorithm, is investigated. Moreover, the normalized channel charge density at collocation points is modeled in terms of its values at the channel bounds through the quasi-static approach. Furthermore, by means of introducing an inverse function for the normalized overdrive channel voltage, the transient terminal currents are formulated as a function of the terminal voltages. In comparison with usual cubic spline collocation structure, the novel model has much better accuracy in its application to EKV structure. The developed model has been applied to the standard 0.15 mm technology and validated by MATLAB R2014a. The obtained results demonstrate that it gives a very high degree of relative accuracy, on average of 99%, for the total time and exhibits absolute error of less than 5% of the maximum value, in its worst case.

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Rakeshkumar Mahto and Reshma John 

Modeling of Photovoltaic Module 

(April 1st 2021)

DOI: 10.5772/intechopen.97082. 

Abstract: A Photovoltaic (PV) cell is a device that converts sunlight or incident light into direct current (DC) based electricity. Among other forms of renewable energy, PV-based power sources are considered a cleaner form of energy generation. Due to lower prices and increased efficiency, they have become much more popular than any other renewable energy source. In a PV module, PV cells are connected in a series and parallel configuration, depending on the voltage and current rating, respectively. Hence, PV modules tend to have a fixed topology. However, in the case of partial shading, mismatching or failure of a single PV cell can lead to many anomalies in a PV module’s functioning. If proper attention is not given, it can lead to the forward biasing of healthy PV cells in the module, causing them to consume the electricity instead of producing it, hence reducing the PV module’s overall efficiency. Hence, to further the PV module research, it is essential to have an approximate way to model them. Doing so allows for understanding the design’s pros and cons before deploying the PV module-based power system in the field. In the last decade, many mathematical models for PV cell simulation and modeling techniques have been proposed. The most popular among all the techniques are diode based PV modeling. In this book chapter, the author will present a double diode based PV cell modeling. Later, the PV module modeling will be presented using these techniques that incorporate mismatch, partial shading, and open/short fault. The partial shading and mismatch are reduced by incorporating a bypass diode along with a group of four PV cells. The mathematical model for showing the effectiveness of bypass diode with PV cells in reducing partial shading effect will also be presented. Additionally, in recent times besides fixed topology of series–parallel, Total Cross-Tied (TCT), Bridge Link (BL), and Honey-Comb (H-C) have shown a better capability in dealing with partial shading and mismatch. The book chapter will also cover PV module modeling using TCT, BL, and H-C in detail.

Available: https://www.intechopen.com/online-first/modeling-of-photovoltaic-module

[paper] ACM) Model in VHDL-AMS

A. S. Kumar, Ch. Rekha, Y. D. S. Raju 

Behavioral Modeling of the Advanced Compact MOSFET (ACM) Model with VHDL-AMS 

OAIJSE, Vol. 6, Issue 1, January 2021 

ISSN (Online) 2456-3293 

*Holymary Institute Of Technology And Science, Bogaram(V), Keesara (M), Hyderabad

Abstract: This paper reports a VHDL-AMS implementation of the Advanced Compact MOSFET (ACM) model. This behavioral model aims at being a reference model for ACM code developers, helping to implement and maintain simulators specic code. Simulation results from classical testbenches are presented and con_rm the correctness of the proposed model.

Fig: The used methodology propose this testbench [ref]

[ref] A. L. T. B. da Fonseca and F. R. de Sousa, "Behavioral modeling of the Advanced Compact MOSFET (ACM) model with VHDL-AMS," 2008 Joint 6th International IEEE Northeast Workshop on Circuits and Systems and TAISA Conference, Montreal, QC, 2008, pp. 169-172

doi: 10.1109/NEWCAS.2008.4606348.

Abstract: This paper reports a VHDL-AMS implementation of the Advanced Compact MOSFET (ACM) model. This behavioral model aims at being a reference model for ACM code developers, helping to implement and maintain simulators specific code. Simulation results from classical testbenches are presented and confirm the correctness of the proposed model.

[paper] Aged MOSFET and Its Compact Modeling

F. A. Herrera, M. Miura-Mattausch, T. Iizuka, H. Kikuchihara, H. J. Mattausch and H. Takatsuka, Universal Feature of Trap-Density Increase in Aged MOSFET and Its Compact Modeling

SISPAD, Kobe, Japan, 2020, pp. 109-112

DOI: 10.23919/SISPAD49475.2020.9241674

Abstract: Our investigation focuses on accurate circuit aging prediction for bulk MOSFETs. A self-consistent aging modeling is proposed, which considers the trap-density Ntrap increase as the aging origin. This Ntrap is considered in the Poisson equation together with other charges induced within MOSFET. It is demonstrated that a universal relationship of the Ntrap increase as a function of integrated substrate current, caused by device stress, can describe the MOSFET aging in a simple way for any device-operating conditions. An exponential increase with constant and unitary slope of the Ntrap is found to successfully predict the aging phenomena, reaching a saturation for high stress degradation. The model universality is verified additionally for any device size. Comparison with existing conventional aging modeling for circuit simulation is discussed for demonstrating the simplifications due to the developed modeling approach

Fig: Schematic of the density-of-state (DOS) model as a function of the state-energy difference from the conduction-band edge, with two parameters gc and Es introduced as new model features.

[paper] Compact Models for Sizing Based on ANN

Husni Habal, Dobroslav Tsonev, Matthias Schweikardt 

Compact Models for Initial MOSFET Sizing Based on Higher-order Artificial Neural Networks

ACM/IEEE Workshop on Machine Learning for CAD (MLCAD ’20)

Nov. 16–20, 2020, Virtual Event, Iceland. ACM, pp. 111-116

DOI: 10.1145/3380446.3430632

¹Infineon Technologies AG Munich, Germany
²LogiqWorks Ltd. Sofia, Bulgaria
³Reutlingen University Reutlingen, Germany

Abstract: Simple MOSFET models intended for hand analysis are inaccurate in deep sub-micrometer process technologies and in the moderate inversion region of device operation. Accurate models, such as BSIM6 model, are too complex for use in hand analysis and are intended for circuit simulators. Artificial neural networks (ANNs) are efficient at capturing both linear and non-linear multivariate relationships. In this work, a straightforward modeling technique is presented using ANNs to replace the BSIM model equations. Existing open-source libraries are used to quickly build models with error rates generally below 3%. When combined with a novel approach, such as the gm/Id systematic design method, the presented models are sufficiently accurate for use in the initial sizing of analog circuit components without simulation.

Figure: ANN Model Architecture.

[paper] Compact Model for Power MOSFET

Abdelghafour Galadi

PSPICE compact model for power MOSFET based on manufacturer datasheet

DOI:10.1088/1757-899X/948/1/012007

National School of Applied Sciences of Safi, Cadi Ayyad University, Marrakech (MA)

Abstract: In this paper, large signal model for power MOSFET devices is presented. The proposed model includes quasi-saturation effect and describes accurately the electrical behavior of the power MOSFET devices. The large signal model elements will be provided based on the device structure. Furthermore, the model parameters are extracted from measurements considering the voltages depending effect of the nonlinear gate-source, gate-drain and drain-source interelectrode capacitances. Excellent agreements will be shown between the simulated and the datasheet data. Finally, a description of the model will be provided along with the parameter extraction procedure.

Fig: a) Conventional power MOSFET structure with b) its subcircuit elements. 

[thesis] RF UTBB FDSOI MOSFET

Vanbrabant, Martin

RF characterization of the back-gate contact on Fully Depleted SOI MOSFETs

http:// hdl.handle.net/2078.1/thesis:26763

Ecole polytechnique de Louvain, Université catholique de Louvain, 2020. 

Academic year 2019–2020: Master in Electrical Engineering

Prom.: Prof. Jean-Pierre Raskin

Readers: Denis Flandre, Valeriya Kilchytska, Lucas Nyssens, Martin Rack

Abstract: Thanks to the thin buried-oxide, the UTBB FDSOI technology with a highly doped region under the BOX is one of the main candidates for future RF applications. One of the most interesting feature of this technology is the possibility to tune the threshold voltage, compensate variability issues and improve the overall device performance. In this work, the impact of the back-gate bias is mainly studied on the threshold voltage and RF FoMs of the front and back-gates.

Figure: Reconstructed (dashed) vs initial (full) Re{Yij} insaturationat VDS=0.8V, VGS=0.8V and VB=0V for a 4-port device.

[paper] RF Small-Signal Model for Four-Port Network MOSFETs

A High-Frequency Small-Signal Model for Four-Port Network MOSFETs

Alejandro Roman-Loera¹, Member, IEEE, Anurag Veerabathini², Member, IEEE, Luis A.Flores-Oropeza¹, Member, IEEE, and Jaime Ramirez-Angulo³, Life Fellow, IEEE

IEEE 63rd IMWSCAS 2020

DOI:10.1109/mwscas48704.2020.9184475 

¹Electronic Systems Department, Universidad Autonoma de Aguascalientes, Mexico.
²Maxim Integrated, Chandler, AZ, USA.
³Klipsch School of Electrical and Computer Engineering, New Mexico State University, Las Cruces, NM, USA.

Abstract: A high-frequency small-signal model for a MOSFET is proposed considering the parasitic capacitances associated with each terminal that is critical in the design of high-frequency amplifiers. The proposed model allows in obtaining a closed form expression for poles and zeros due to parasitic elements along with the conventional poles and zeros. This model gives an additional degree of freedom in choosing the location of poles and zeros to improve the frequency response. The proposed high-frequency small-signal model for MOSFET is validated in simulation by implementing a high-frequency voltage follower in 0.18µm CMOS process. The proposed model shows the existence of a zero in a voltage follower that is introduced by the parasitic elements at high-frequencies and it is validated with implementation.

Fig: Small signal equivalent circuit of a 4-port MOSFET (a) Conventional model, (b) Model with substrate parasitics, and (c) Model with additional parasitics, and (d) Proposed model.

Acknowledgment: This work has been supported by PRODEP program from SEP (Secretariat of Public Education, Mexico) and Universidad Autonoma de Aguascalientes, Aguascalientes, Mexico.

[paper] GCC Method for Determining MOSFET VTH

Matthias Bucher¹, Nikolaos Makris¹, Loukas Chevas¹

Generalized Constant Current Method for Determining MOSFET Threshold Voltage

arXiv:2008.00576v1 (2 Aug 202) 

has been submitted to the IEEE for possible publication

¹ School of Electrical and Computer Engineering, Technical University of Crete

Abstract: A novel method for extracting threshold voltage (VTH) and substrate effect parameters of MOSFETs with constant current bias at all levels of inversion is presented. This generalized constant-current (GCC) method exploits the charge-based model of MOSFETs to extract threshold voltage and other substrate-effect related parameters. The method is applicable over a wide range of current throughout weak and moderate inversion and to some extent in strong inversion. This method is particularly useful when applied for MOSFETs presenting edge conduction effect (subthreshold hump) in CMOS processes using Shallow Trench Isolation (STI).

Fig:  Application of the GCC method in presence of edge conduction phenomenon in STI MOSFETs. A constant current is applied to determine pinchoff voltage for the center transistor in moderate inversion at IC=2. To characterize the edge transistor, imposing a current criterion IC=1E−4 corresponds to ICe≈0.02. Pinchoff voltage (VP) and slope factor n characteristics illustrate the determination of parameters for center and edge transistors.

Acknowledgment: This work was partly supported under Project INNOVATION-EL-Crete

(MIS 5002772).

[paper] SiC MOSFET SPICE Model

Lefdal Hove, Haavard, Ole Christian Spro, Giuseppe Guidi

and Dimosthenis Peftitsis

Improved SiC MOSFET SPICE Model to Avoid Convergence Errors

Materials Science Forum 1004 (July 2020): 856–64

DOI: 10.4028/www.scientific.net/msf.1004.856

Abstract: This paper presents improvements to a SPICE model for a commercially available SiC MOSFET to avoid convergence errors while still providing reliable simulation results. Functionality in the internal part of the model that shapes the transconductance of the device according to its junction temperature and gate-source voltage dependency has been improved to provide a continuous characteristic rather than the initial discontinuous performance. Furthermore, the output characteristics from the initial and the proposed model have been compared to lab measurements of an actual device. The results show that the proposed and initial model provide equally reliable simulation results. However, the proposed model does not run into convergence problems.

References 

[1] X. She, A. Huang, O. Lucia, and B. Ozpineci, Review of Silicon Carbide Power Devices and Their Applications, IEEE Transactions on Industrial Electronics, vol. 64, no. 10, p.8193–8205, (2017).

[2] J. Rabkowski, D. Peftitsis, and H. P. Nee, Silicon carbide power transistors: A new era in power electronics is initiated, IEEE Industrial Electronics Magazine, vol. 6, no. 2, p.17–26, (2012).

[3] A. Stefanskyi, L. Starzak, A. Napieralski, and M. Lobur, Analysis of SPICE models for SiC MOSFET power devices,, 2017 14th CADSM 2017 - Proceedings, p.79–81, (2017).

[4] H. L. Hove, O. C. Spro, D. Peftitsis, G. Guidi, and K. Ljøkelsøy, Minimization of dead time effect on bridge converter output voltage quality by use of advanced gate drivers, 2019 10th ICPE 2019 ECCE Asia, (2019).

[5] N. Mohan, T. Undeland, and W. Robbins, Power Electronics; Converters, Applications, and Design, third ed., Wiley, (2003).

[6] C. Enz, F. Krummenacher, and E. Vittoz, An Analytical MOS Transistor Model Valid in All Regions of Operation and Dedicated to Low-Voltage and Low-Current Application, Analog Integrated Circuits and Signal Processing, vol. 8, p.83–114, (1995).

[7] M. Bucher, C. Lallement, C. Enz, F. Théodoloz, and F. Krummenacher, The EPFL-EKV MOSFET Model Equations for Simulation Technical Report V2.6,, EPFL, Lausanne, Switzerland, (1999).

[8] B. N. Pushpakaran, S. B. Bayne, G. Wang, and J. Mookken, Fast and accurate electro-thermal behavioral model of a commercial SiC 1200V, 80 mΩ power MOSFET,, Digest of Technical Papers IEEE IPPC, vol. 2015-Octob, p.1–5, (2015).

[paper] Vertical III-V Nanowire MOSFETs on Si

Olli-Pekka Kilpi, Markus Hellenbrand, Johannes Svensson, Axel R. Persson, Reine Wallenberg, Erik Lind, Member, IEEE, and Lars-Erik Wernersson

High-Performance Vertical III-V Nanowire MOSFETs on Si With gm > 3 mS/μm

in IEEE EDL vol. 41, no. 8, pp. 1161-1164, Aug. 2020

DOI: 10.1109/LED.2020.3004716

Abstract: Vertical III-V nanowire MOSFETs have demonstrated excellent performance including high transconductance and high Ion. One main bottleneck for the vertical MOSFETs is the large access resistance arising from the contacts and ungated regions. We demonstrate a process to reduce the access resistance by combining a gate-last process with ALD gate-metal deposition. The devices demonstrate fully scalable gm down to Lg = 25 nm. These vertical core/shell InAs/InGaAs MOSFETs demonstrate gm = 3.1 mS/μm and Ron = 190 μm. This is the highest gm demonstrated on Si. Transmission line measurement verifies a low contact resistance with RC = 115 μm, demonstrating that most of the MOSFET access resistance is located in the contact regions.

FIG: (a) of the MOSFET structure demonstrating benefit of the TiN gate metal;

(b )output characteristics of the vertical nanowire MOSFET 

with 90 nanowires, LG = 25 nm and diameter 17 nm.

Acknowledgment: This work was supported in part by the Swedish Research Council, in part by the Knut and Alice Wallenberg Foundation, in part by the Swedish Foundation for Strategic Research, and in part by the European Union H2020 Program INSIGHT under Grant 688784.

[paper] Compact Modeling of Parasitic FET capacitance

Sharma, S. M., Singh, A., Dasgupta, S., & Kartikeyan, M. V. 

A review on the compact modeling of parasitic capacitance: 

from basic to advanced FETs. 

Journal of Computational Electronics

DOI: 10.1007/s10825-020-01515-4

Abstract: This paper presents a review on the development of parasitic-capacitance modeling for metal–oxide–semiconductor feldefect transistors (MOSFETs), covering models developed for the simple parallel-plate capacitance and the nonplanar and coplanar plate capacitances required for the intrinsic and extrinsic part of such devices. A comparative study of various extrinsic capacitance models with respect to a reference model is used to analyze the benefts of the various approaches. Capacitance models for basic MOSFETs and advance multigate FETs with two-dimensional (2D) and three-dimensional (3D) structures are reviewed. It is found that the elliptical feld lines between the gate electrodes and source/drain region are modeled very well, while deviations of ±2% in the orthogonal plate capacitance are observed when the gate electrode thickness is varied from 5 to 20nm.

Fig: The 3D structure of a FinFET

Acknowledgements: The authors would like to thank the Department of Electronics and Communication Engineering, IIT Roorkee, for their valuable support in carrying out this research work.

[paper] “Extrinsic” Compact Model of the MOSFET Drain Current

V. O. Turin, R. S. Shkarlat, G. I. Zebrev, B. Iñiguez and M. S. Shur

The “Extrinsic” Compact Model of the MOSFET Drain Current Based on a New Interpolation Expression for the Transition Between Linear and Saturation Regimes with a Monotonic Decrease of the Differential Conductance to a Nonzero Value

2020 4th IEEE EDTM, Penang, Malaysia

2020, pp. 1-4

doi: 10.1109/EDTM47692.2020.9117810

Abstract: Previously, we proposed a new interpolation expression to bridge the transition between the linear and the saturation regimes of “intrinsic” MOSFET. This approach, in contrast to the traditional one, gives a monotonic decrease of the differential conductance from the maximum value in the linear regime to the minimum value in the saturation regime. Later, we proposed a linear approximation for an “extrinsic” MOSFET drain current dependence on the “extrinsic” drain bias in the saturation regime for not very high drain bias when nonlinear effects can be neglected. To obtain this approximation, an equation for the output differential resistance of the “extrinsic” MOSFET in saturation regime was obtained, that is similar to the result known from the theory of the common source MOSFET amplifier with source degeneration. In this paper, we combine these two results and present an “extrinsic” compact model for a short-channel MOSFET above threshold drain current with proper account of the differential conductance in the saturation regime.