Showing posts with label 4-pots. Show all posts
Showing posts with label 4-pots. Show all posts

Sep 29, 2020

[thesis] RF UTBB FDSOI MOSFET

Vanbrabant, Martin
RF characterization of the back-gate contact on Fully Depleted SOI MOSFETs
http:// hdl.handle.net/2078.1/thesis:26763
Ecole polytechnique de Louvain, Université catholique de Louvain, 2020. 
Academic year 2019–2020: Master in Electrical Engineering
Prom.: Prof. Jean-Pierre Raskin
Readers: Denis Flandre, Valeriya Kilchytska, Lucas Nyssens, Martin Rack

Abstract: Thanks to the thin buried-oxide, the UTBB FDSOI technology with a highly doped region under the BOX is one of the main candidates for future RF applications. One of the most interesting feature of this technology is the possibility to tune the threshold voltage, compensate variability issues and improve the overall device performance. In this work, the impact of the back-gate bias is mainly studied on the threshold voltage and RF FoMs of the front and back-gates.


Figure: Reconstructed (dashed) vs initial (full) Re{Yij} insaturationat VDS=0.8V, VGS=0.8V and VB=0V for a 4-port device.