Showing posts with label four-port network. Show all posts
Showing posts with label four-port network. Show all posts

Sep 8, 2020

[paper] RF Small-Signal Model for Four-Port Network MOSFETs

A High-Frequency Small-Signal Model for Four-Port Network MOSFETs
Alejandro Roman-Loera1, Member, IEEE, Anurag Veerabathini2, Member, IEEE, Luis A.Flores-Oropeza1, Member, IEEE, and Jaime Ramirez-Angulo3, Life Fellow, IEEE
IEEE 63rd IMWSCAS 2020
DOI:10.1109/mwscas48704.2020.9184475 

1Electronic Systems Department, Universidad Autonoma de Aguascalientes, Mexico.
2Maxim Integrated, Chandler, AZ, USA.
3Klipsch School of Electrical and Computer Engineering, New Mexico State University, Las Cruces, NM, USA.

Abstract: A high-frequency small-signal model for a MOSFET is proposed considering the parasitic capacitances associated with each terminal that is critical in the design of high-frequency amplifiers. The proposed model allows in obtaining a closed form expression for poles and zeros due to parasitic elements along with the conventional poles and zeros. This model gives an additional degree of freedom in choosing the location of poles and zeros to improve the frequency response. The proposed high-frequency small-signal model for MOSFET is validated in simulation by implementing a high-frequency voltage follower in 0.18µm CMOS process. The proposed model shows the existence of a zero in a voltage follower that is introduced by the parasitic elements at high-frequencies and it is validated with implementation.

Fig: Small signal equivalent circuit of a 4-port MOSFET (a) Conventional model, (b) Model with substrate parasitics, and (c) Model with additional parasitics, and (d) Proposed model.

Acknowledgment: This work has been supported by PRODEP program from SEP (Secretariat of Public Education, Mexico) and Universidad Autonoma de Aguascalientes, Aguascalientes, Mexico.